# Hierarchical schematics

Depending on what you want to achieve, there are several options how to use hierarchy. If you are unsure, ask yourself if you want to include a subcircuit multiple times in your design, or want to represent a subsheet as a symbol in another sheet. If you answer either with yes, go with full mangling. If not, you probably don't need hierarchy at all and can just use multiple schematic files.

The schematic hierarchy isn't limited to one level—subcircuits can in turn contain other subcircuits.

## Multiple schematic files

If you just want to split your schematic to multiple pages, you don't need to use hierarchy at all. Just list the individual schematic files when invoking gnetlist:

    $ gnetlist -g geda page-one.sch page-two.sch

If you are using the same `netname=` attribute on different pages, the nets will automatically be connected.

## Hierarchy as a convenience method

Alternatively, you can create a top schematic which contains symbols for each subsheet and tell `gnetlist` to go look for the corresponding schematic files. You do so by adding a `source=` attribute to the symbol and adding the directory which contains the subsheets to the source library. Usually this will be the same directory as the schematic containing the subsheet symbol, so add the following line to `gnetlistrc` (either your global one in `~/.gEDA/`, or a project-specific one in the same directory):

    (source-library ".")

You also need to tell gnetlist to disable component and net name mangling or you will end up with component names like `U?/R1`, and your nets will not connect. To do so, add the following lines to `gnetlistrc`:

    (hierarchy-netattrib-mangle "disabled")
    (hierarchy-netname-mangle "disabled")
    (hierarchy-uref-mangle "disabled")

Now when invoking gnetlist, just specify the main schematic file:

    $ gnetlist -g geda main.sch

This will only work if the configuration setting `gnetlist.traverse-hierarchy` is set to `true`. This is the default but may have been overridden by your distribution or local administrator.
`gnetlist` will complain if the subsheet symbols don't contain a `refdes=` attribute, but with mangling disabled, it won't use it in any way.

In `gschem`, you can navigate the schematic hierarchy using the commands from the “Hierarchy” menu. To view the underlying schematic for a subcircuit component, select it and use Hierarchy→Down Schematic. Once finished editing, use Hierarchy→Up to return to the original schematic. (This works only if you accessed the subcircuit's schematic in that way.) Analogously, you can edit the subcircuit symbol itself using Hierarchy→Down Symbol.

As an alternative to using the same net name, you can add pins to a subsheet symbol to route nets to and from that schematic. See the section Input/output pins below for details.

## Hierarchy as a grouping/instantiation mechanism

If you want to include a subcircuit multiple times in your schematic, you need a way to tell the components of one instantiation from those of another one (given that your subcircuit contains any components). This is where refdef mangling comes in. You enable it by specifying

    (hierarchy-uref-mangle "enabled")

in `gnetlistrc`. Now, `gnetlist` constructs the name of an instantiated component by appending it to the subsheet symbol's `refdes=` attribute, separated by a slash. You can configure this in `gnetlistrc`. For example, to list the component `refdes=` first and use a colon as a separator, use

    (hierarchy-uref-order "prepend")
    (hierarchy-uref-separator ":")

Named nets from one instantiation will connect to the same net of another one. This means you can't use net names to connect (non-power) pins across the hierarchy any more; you need I/O pins instead. Also, you will probably want to use separate net namespaces so you don't short-circuit nets between instantiations when using net names.

### Input/output pins

In order to connect a net to a subcircuit, you need to add a pin to the subcircuit symbol and a corresponding footprint-less I/O component to the subcircuit whose `refdes=` matches the `pinlabel=` of the pin. During netlist generation, these two nets will be connected. (You can normally use the `in-1.sym` and `out-1.sym` symbols from the generic “Input/Output” symbol library for this.)

If you get an error about a “Missing I/O symbol”, make sure you set a `refdes=` for the subsheet symbols.
Make sure not to add more than one I/O symbol for each pin as this will silently produce an incorrect netlist.

## Separating net=/netname= namespaces

The typical and cleanest way to use hierarchy is to enable both refdes and net=/netname= mangling. This means that the subcircuit lives in a namespace of its own, and the only way to connect nets between the instantiating and the instantiated schematic is through pins of the subsheet symbol and I/O ports in its schematic. If you want to include a subcircuit multiple times in your design, even though it's not strictly necessary, this is the recommended way to use hierarchy, as you would otherwise have to be very careful about avoiding naming nets in the subschematic which would cause them to be silently short-circuited between instantiations.

You enable net=/netname= mangling it by specifying

    (hierarchy-netattrib-mangle "enabled")
    (hierarchy-netname-mangle "enabled")

in `gnetlistrc`. As with refdes mangling, you can also configure the way mangled net names are constructed.

### netname= mangling vs. net= mangling

There are two slightly different options which influence net namespaces: `netname=` mangling means that net names set via the `netname=` attribute on nets are prefixed or suffixed with the subsheet instance's hierarchy tag. `net=` attribute mangling means that net names which are set via the `net=` attribute on components (like, for example, `Vcc` and `GND` pins in some libraries) are prefixed or suffixed with the subsheet instance's hierarchy tag.

Usually, when using net namespaces, you would enable both `netname=` and `net=` mangling. Depending on how you use hierarchy in your design, there might be use cases where you might want to disable one of them, though: If you disable `netname=` mangling, you gain the ability to use global net names and connect nets across the hierarchy by setting the `netname=` attribute while still having implicit nets separate. If you disable `net=` mangling, all implicit pins (usually power and ground pins) across all of your schematic pages will be connected, so you don't have to use explicit power and ground pins on your subsheet symbols. Both approaches come at the cost of reduced readability, though: you can't tell any more how a subsheet is connected to the rest of the design by just looking at the schematic.