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armreg.h
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1 /* $NetBSD: armreg.h,v 1.124 2018/08/15 06:13:56 skrll Exp $ */
2 
3 /*
4  * Copyright (c) 1998, 2001 Ben Harris
5  * Copyright (c) 1994-1996 Mark Brinicombe.
6  * Copyright (c) 1994 Brini.
7  * All rights reserved.
8  *
9  * This code is derived from software written for Brini by Mark Brinicombe
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  * notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  * notice, this list of conditions and the following disclaimer in the
18  * documentation and/or other materials provided with the distribution.
19  * 3. All advertising materials mentioning features or use of this software
20  * must display the following acknowledgement:
21  * This product includes software developed by Brini.
22  * 4. The name of the company nor the name of the author may be used to
23  * endorse or promote products derived from this software without specific
24  * prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
27  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
28  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
30  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36  * SUCH DAMAGE.
37  */
38 
39 #ifndef _ARM_ARMREG_H
40 #define _ARM_ARMREG_H
41 
42 // #include <arm/cputypes.h>
44 
45 // #ifdef __arm__
46 
47 /*
48  * ARM Process Status Register
49  *
50  * The picture in the ARM manuals looks like this:
51  * 3 3 2 2 2 2
52  * 1 0 9 8 7 6 8 7 6 5 4 0
53  * +-+-+-+-+-+-------------------------------------+-+-+-+---------+
54  * |N|Z|C|V|Q| reserved |I|F|T|M M M M M|
55  * | | | | | | | | | |4 3 2 1 0|
56  * +-+-+-+-+-+-------------------------------------+-+-+-+---------+
57  */
58 
59 #define PSR_FLAGS 0xf0000000 /* flags */
60 #define PSR_N_bit (1 << 31) /* negative */
61 #define PSR_Z_bit (1 << 30) /* zero */
62 #define PSR_C_bit (1 << 29) /* carry */
63 #define PSR_V_bit (1 << 28) /* overflow */
64 
65 #define PSR_Q_bit (1 << 27) /* saturation */
66 #define PSR_IT1_bit (1 << 26)
67 #define PSR_IT0_bit (1 << 25)
68 #define PSR_J_bit (1 << 24) /* Jazelle mode */
69 #define PSR_GE_bits (15 << 16) /* SIMD GE bits */
70 #define PSR_IT7_bit (1 << 15)
71 #define PSR_IT6_bit (1 << 14)
72 #define PSR_IT5_bit (1 << 13)
73 #define PSR_IT4_bit (1 << 12)
74 #define PSR_IT3_bit (1 << 11)
75 #define PSR_IT2_bit (1 << 10)
76 #define PSR_E_BIT (1 << 9) /* Endian state */
77 #define PSR_A_BIT (1 << 8) /* Async abort disable */
78 
79 #define I32_bit (1 << 7) /* IRQ disable */
80 #define F32_bit (1 << 6) /* FIQ disable */
81 #define IF32_bits (3 << 6) /* IRQ/FIQ disable */
82 
83 #define PSR_T_bit (1 << 5) /* Thumb state */
84 
85 #define PSR_MODE 0x0000001f /* mode mask */
86 #define PSR_USR32_MODE 0x00000010
87 #define PSR_FIQ32_MODE 0x00000011
88 #define PSR_IRQ32_MODE 0x00000012
89 #define PSR_SVC32_MODE 0x00000013
90 #define PSR_MON32_MODE 0x00000016
91 #define PSR_ABT32_MODE 0x00000017
92 #define PSR_HYP32_MODE 0x0000001a
93 #define PSR_UND32_MODE 0x0000001b
94 #define PSR_SYS32_MODE 0x0000001f
95 #define PSR_32_MODE 0x00000010
96 
97 #define R15_FLAGS 0xf0000000
98 #define R15_FLAG_N 0x80000000
99 #define R15_FLAG_Z 0x40000000
100 #define R15_FLAG_C 0x20000000
101 #define R15_FLAG_V 0x10000000
102 
103 /*
104  * Co-processor 15: The system control co-processor.
105  */
106 
107 #define ARM_CP15_CPU_ID 0
108 
109 /* CPUID registers */
110 #define ARM_ISA3_SYNCHPRIM_MASK 0x0000f000
111 #define ARM_ISA4_SYNCHPRIM_MASK 0x00f00000
112 #define ARM_ISA3_SYNCHPRIM_LDREX 0x10 // LDREX
113 #define ARM_ISA3_SYNCHPRIM_LDREXPLUS 0x13 // +CLREX/LDREXB/LDREXH
114 #define ARM_ISA3_SYNCHPRIM_LDREXD 0x20 // +LDREXD
115 #define ARM_PFR0_THUMBEE_MASK 0x0000f000
116 #define ARM_PFR1_GTIMER_MASK 0x000f0000
117 #define ARM_PFR1_VIRT_MASK 0x0000f000
118 #define ARM_PFR1_SEC_MASK 0x000000f0
119 
120 /* Media and VFP Feature registers */
121 #define ARM_MVFR0_ROUNDING_MASK 0xf0000000
122 #define ARM_MVFR0_SHORTVEC_MASK 0x0f000000
123 #define ARM_MVFR0_SQRT_MASK 0x00f00000
124 #define ARM_MVFR0_DIVIDE_MASK 0x000f0000
125 #define ARM_MVFR0_EXCEPT_MASK 0x0000f000
126 #define ARM_MVFR0_DFLOAT_MASK 0x00000f00
127 #define ARM_MVFR0_SFLOAT_MASK 0x000000f0
128 #define ARM_MVFR0_ASIMD_MASK 0x0000000f
129 #define ARM_MVFR1_ASIMD_FMACS_MASK 0xf0000000
130 #define ARM_MVFR1_VFP_HPFP_MASK 0x0f000000
131 #define ARM_MVFR1_ASIMD_HPFP_MASK 0x00f00000
132 #define ARM_MVFR1_ASIMD_SPFP_MASK 0x000f0000
133 #define ARM_MVFR1_ASIMD_INT_MASK 0x0000f000
134 #define ARM_MVFR1_ASIMD_LDST_MASK 0x00000f00
135 #define ARM_MVFR1_D_NAN_MASK 0x000000f0
136 #define ARM_MVFR1_FTZ_MASK 0x0000000f
137 
138 /* ARM3-specific coprocessor 15 registers */
139 #define ARM3_CP15_FLUSH 1
140 #define ARM3_CP15_CONTROL 2
141 #define ARM3_CP15_CACHEABLE 3
142 #define ARM3_CP15_UPDATEABLE 4
143 #define ARM3_CP15_DISRUPTIVE 5
144 
145 /* ARM3 Control register bits */
146 #define ARM3_CTL_CACHE_ON 0x00000001
147 #define ARM3_CTL_SHARED 0x00000002
148 #define ARM3_CTL_MONITOR 0x00000004
149 
150 /*
151  * Post-ARM3 CP15 registers:
152  *
153  * 1 Control register
154  *
155  * 2 Translation Table Base
156  *
157  * 3 Domain Access Control
158  *
159  * 4 Reserved
160  *
161  * 5 Fault Status
162  *
163  * 6 Fault Address
164  *
165  * 7 Cache/write-buffer Control
166  *
167  * 8 TLB Control
168  *
169  * 9 Cache Lockdown
170  *
171  * 10 TLB Lockdown
172  *
173  * 11 Reserved
174  *
175  * 12 Reserved
176  *
177  * 13 Process ID (for FCSE)
178  *
179  * 14 Reserved
180  *
181  * 15 Implementation Dependent
182  */
183 
184 /* Some of the definitions below need cleaning up for V3/V4 architectures */
185 
186 /* CPU control register (CP15 register 1) */
187 #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */
188 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
189 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */
190 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
191 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
192 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
193 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
194 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
195 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
196 #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */
197 #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */
198 #define CPU_CONTROL_SWP_ENABLE 0x00000400 /* SW: SWP{B} perform normally. */
199 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
200 #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */
201 #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */
202 #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */
203 #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */
204 #define CPU_CONTROL_HA_ENABLE 0x00020000 /* HA: Hardware Access flag enable */
205 #define CPU_CONTROL_WXN_ENABLE 0x00080000 /* WXN: Write Execute Never */
206 #define CPU_CONTROL_UWXN_ENABLE 0x00100000 /* UWXN: User Write eXecute Never */
207 #define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */
208 #define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */
209 #define CPU_CONTROL_XP_ENABLE 0x00800000 /* XP: extended page table */
210 #define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */
211 #define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */
212 #define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */
213 #define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: */
214 #define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access flag enable */
215 #define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */
216 
217 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
218 
219 /* ARMv6/ARMv7 Co-Processor Access Control Register (CP15, 0, c1, c0, 2) */
220 #define CPACR_V7_ASEDIS 0x80000000 /* Disable Advanced SIMD Ext. */
221 #define CPACR_V7_D32DIS 0x40000000 /* Disable VFP regs 15-31 */
222 #define CPACR_CPn(n) (3 << (2*n))
223 #define CPACR_NOACCESS 0 /* reset value */
224 #define CPACR_PRIVED 1 /* Privileged mode access */
225 #define CPACR_RESERVED 2
226 #define CPACR_ALL 3 /* Privileged and User mode access */
227 
228 /* ARMv6/ARMv7 Non-Secure Access Control Register (CP15, 0, c1, c1, 2) */
229 #define NSACR_SMP 0x00040000 /* ACTRL.SMP is writeable (!A8) */
230 #define NSACR_L2ERR 0x00020000 /* L2ECTRL is writeable (!A8) */
231 #define NSACR_ASEDIS 0x00008000 /* Deny Advanced SIMD Ext. */
232 #define NSACR_D32DIS 0x00004000 /* Deny VFP regs 15-31 */
233 #define NSACR_CPn(n) (1 << (n)) /* NonSecure access allowed */
234 
235 /* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */
236 #define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */
237 #define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */
238 #define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */
239 #define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */
240 #define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */
241 #define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */
242 #define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */
243 #define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */
244 
245 /* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */
246 #define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */
247  /* This is an undocumented flag
248  * used to work around a cache bug
249  * in r0 steppings. See errata
250  * 364296.
251  */
252 /* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */
253 #define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */
254 #define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */
255 #define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */
256 #define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */
257 
258 /* XScale Auxiliary Control Register (CP15 register 1, opcode2 1) */
259 #define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */
260 #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */
261 #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */
262 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */
263 #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */
264 #define XSCALE_AUXCTL_MD_MASK 0x00000030
265 
266 /* ARM11 MPCore Auxiliary Control Register (CP15 register 1, opcode2 1) */
267 #define MPCORE_AUXCTL_RS 0x00000001 /* return stack */
268 #define MPCORE_AUXCTL_DB 0x00000002 /* dynamic branch prediction */
269 #define MPCORE_AUXCTL_SB 0x00000004 /* static branch prediction */
270 #define MPCORE_AUXCTL_F 0x00000008 /* instruction folding enable */
271 #define MPCORE_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */
272 #define MPCORE_AUXCTL_SA 0x00000020 /* SMP/AMP */
273 
274 /* Marvell PJ4B Auxillary Control Register (CP15.0.R1.c0.1) */
275 #define PJ4B_AUXCTL_FW __BIT(0) /* Cache and TLB updates broadcast */
276 #define PJ4B_AUXCTL_SMPNAMP __BIT(6) /* 0 = AMP, 1 = SMP */
277 #define PJ4B_AUXCTL_L1PARITY __BIT(9) /* L1 parity checking */
278 
279 /* Marvell PJ4B Auxialiary Function Modes Control 0 (CP15.1.R15.c2.0) */
280 #define PJ4B_AUXFMC0_L2EN __BIT(0) /* Tightly-Coupled L2 cache enable */
281 #define PJ4B_AUXFMC0_SMPNAMP __BIT(1) /* 0 = AMP, 1 = SMP */
282 #define PJ4B_AUXFMC0_L1PARITY __BIT(2) /* alias of PJ4B_AUXCTL_L1PARITY */
283 #define PJ4B_AUXFMC0_DCSLFD __BIT(2) /* Disable DC Speculative linefill */
284 #define PJ4B_AUXFMC0_FW __BIT(8) /* alias of PJ4B_AUXCTL_FW*/
285 
286 /* Cortex-A5 Auxiliary Control Register (CP15 register 1, opcode 1) */
287 #define CORTEXA5_ACTLR_FW __BIT(0)
288 #define CORTEXA5_ACTLR_SMP __BIT(6) /* Inner Cache Shared is cacheable */
289 #define CORTEXA5_ACTLR_EXCL __BIT(7) /* Exclusive L1/L2 cache control */
290 
291 /* Cortex-A7 Auxiliary Control Register (CP15 register 1, opcode 1) */
292 #define CORTEXA7_ACTLR_L1ALIAS __BIT(0) /* Enables L1 cache alias checks */
293 #define CORTEXA7_ACTLR_L2EN __BIT(1) /* Enables L2 cache */
294 #define CORTEXA7_ACTLR_SMP __BIT(6) /* SMP */
295 
296 /* Cortex-A8 Auxiliary Control Register (CP15 register 1, opcode 1) */
297 #define CORTEXA8_ACTLR_L1ALIAS __BIT(0) /* Enables L1 cache alias checks */
298 #define CORTEXA8_ACTLR_L2EN __BIT(1) /* Enables L2 cache */
299 
300 /* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */
301 #define CORTEXA9_AUXCTL_FW 0x00000001 /* Cache and TLB updates broadcast */
302 #define CORTEXA9_AUXCTL_L2PE 0x00000002 /* Prefetch hint enable */
303 #define CORTEXA9_AUXCTL_L1PE 0x00000004 /* Data prefetch hint enable */
304 #define CORTEXA9_AUXCTL_WR_ZERO 0x00000008 /* Ena. write full line of 0s mode */
305 #define CORTEXA9_AUXCTL_SMP 0x00000040 /* Coherency is active */
306 #define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache bit */
307 #define CORTEXA9_AUXCTL_ONEWAY 0x00000100 /* Allocate in on cache way only */
308 #define CORTEXA9_AUXCTL_PARITY 0x00000200 /* Support parity checking */
309 
310 /* Cortex-A15 Auxiliary Control Register (CP15 register 1, opcode 1) */
311 #define CORTEXA15_ACTLR_BTB __BIT(0) /* Cache and TLB updates broadcast */
312 #define CORTEXA15_ACTLR_SMP __BIT(6) /* SMP */
313 #define CORTEXA15_ACTLR_IOBEU __BIT(15) /* In order issue in Branch Exec Unit */
314 #define CORTEXA15_ACTLR_SDEH __BIT(31) /* snoop-delayed exclusive handling */
315 
316 /* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */
317 #define FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */
318 #define FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */
319 #define FC_WR_ALLOC_EN 0x10000000 /* Enable Write Allocate */
320 #define FC_L2_PREF_DIS 0x01000000 /* L2 Cache Prefetch Disable */
321 #define FC_L2_INV_EVICT_LINE 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */
322 #define FC_L2CACHE_EN 0x00400000 /* L2 enable */
323 #define FC_ICACHE_REPL_LOCK 0x00080000 /* Replace ICache Lock */
324 #define FC_GLOB_HIST_REG_EN 0x00040000 /* Branch Global History Register Enable */
325 #define FC_BRANCH_TARG_BUF_DIS 0x00020000 /* Branch Target Buffer Disable */
326 #define FC_L1_PAR_ERR_EN 0x00010000 /* L1 Parity Error Enable */
327 
328 /* Cache type register definitions 0 */
329 #define CPU_CT_FORMAT(x) (((x) >> 29) & 0x7) /* reg format */
330 #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */
331 #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */
332 #define CPU_CT_S (1U << 24) /* split cache */
333 #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */
334 
335 #define CPU_CT_CTYPE_WT 0 /* write-through */
336 #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */
337 #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */
338 #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */
339 #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */
340 #define CPU_CT_CTYPE_WB14 14 /* w/b, cp15,7, lockdown fmt C */
341 
342 #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */
343 #define CPU_CT_xSIZE_M (1U << 2) /* multiplier */
344 #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */
345 #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */
346 #define CPU_CT_xSIZE_P (1U << 11) /* need to page-color */
347 
348 /* format 4 definitions */
349 #define CPU_CT4_ILINE(x) ((x) & 0xf) /* I$ line size */
350 #define CPU_CT4_DLINE(x) (((x) >> 16) & 0xf) /* D$ line size */
351 #define CPU_CT4_L1IPOLICY(x) (((x) >> 14) & 0x3) /* I$ policy */
352 #define CPU_CT4_L1_AIVIVT 1 /* ASID tagged VIVT */
353 #define CPU_CT4_L1_VIPT 2 /* VIPT */
354 #define CPU_CT4_L1_PIPT 3 /* PIPT */
355 #define CPU_CT4_ERG(x) (((x) >> 20) & 0xf) /* Cache WriteBack Granule */
356 #define CPU_CT4_CWG(x) (((x) >> 24) & 0xf) /* Exclusive Resv. Granule */
357 
358 /* Cache size identifaction register definitions 1, Rd, c0, c0, 0 */
359 #define CPU_CSID_CTYPE_WT 0x80000000 /* write-through avail */
360 #define CPU_CSID_CTYPE_WB 0x40000000 /* write-back avail */
361 #define CPU_CSID_CTYPE_RA 0x20000000 /* read-allocation avail */
362 #define CPU_CSID_CTYPE_WA 0x10000000 /* write-allocation avail */
363 #define CPU_CSID_NUMSETS(x) (((x) >> 13) & 0x7fff)
364 #define CPU_CSID_ASSOC(x) (((x) >> 3) & 0x1ff)
365 #define CPU_CSID_LEN(x) ((x) & 0x07)
366 
367 /* Cache size selection register definitions 2, Rd, c0, c0, 0 */
368 #define CPU_CSSR_L2 0x00000002
369 #define CPU_CSSR_L1 0x00000000
370 #define CPU_CSSR_InD 0x00000001
371 
372 /* Fault status register definitions */
373 
374 #define FAULT_TYPE_MASK 0x0f
375 #define FAULT_USER 0x10
376 
377 #define FAULT_WRTBUF_0 0x00 /* Vector Exception */
378 #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */
379 #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */
380 #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */
381 #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */
382 #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */
383 #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */
384 #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */
385 #define FAULT_ALIGN_0 0x01 /* Alignment */
386 #define FAULT_ALIGN_1 0x03 /* Alignment */
387 #define FAULT_TRANS_S 0x05 /* Translation -- Section */
388 #define FAULT_TRANS_P 0x07 /* Translation -- Page */
389 #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */
390 #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */
391 #define FAULT_PERM_S 0x0d /* Permission -- Section */
392 #define FAULT_PERM_P 0x0f /* Permission -- Page */
393 
394 #define FAULT_LPAE 0x0200 /* (SW) used long descriptors */
395 #define FAULT_IMPRECISE 0x0400 /* Imprecise exception (XSCALE) */
396 #define FAULT_WRITE 0x0800 /* fault was due to write (ARMv6+) */
397 #define FAULT_EXT 0x1000 /* fault was due to external abort (ARMv6+) */
398 #define FAULT_CM 0x2000 /* fault was due to cache maintenance (ARMv7+) */
399 
400 /*
401  * Address of the vector page, low and high versions.
402  */
403 #define ARM_VECTORS_LOW 0x00000000U
404 #define ARM_VECTORS_HIGH 0xffff0000U
405 
406 /*
407  * ARM Instructions
408  *
409  * 3 3 2 2 2
410  * 1 0 9 8 7 0
411  * +-------+-------------------------------------------------------+
412  * | cond | instruction dependent |
413  * |c c c c| |
414  * +-------+-------------------------------------------------------+
415  */
416 
417 #define INSN_SIZE 4 /* Always 4 bytes */
418 #define INSN_COND_MASK 0xf0000000 /* Condition mask */
419 #define INSN_COND_EQ 0 /* Z == 1 */
420 #define INSN_COND_NE 1 /* Z == 0 */
421 #define INSN_COND_CS 2 /* C == 1 */
422 #define INSN_COND_CC 3 /* C == 0 */
423 #define INSN_COND_MI 4 /* N == 1 */
424 #define INSN_COND_PL 5 /* N == 0 */
425 #define INSN_COND_VS 6 /* V == 1 */
426 #define INSN_COND_VC 7 /* V == 0 */
427 #define INSN_COND_HI 8 /* C == 1 && Z == 0 */
428 #define INSN_COND_LS 9 /* C == 0 || Z == 1 */
429 #define INSN_COND_GE 10 /* N == V */
430 #define INSN_COND_LT 11 /* N != V */
431 #define INSN_COND_GT 12 /* Z == 0 && N == V */
432 #define INSN_COND_LE 13 /* Z == 1 || N != V */
433 #define INSN_COND_AL 14 /* Always condition */
434 
435 #define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */
436 
437 /*
438  * Defines and such for arm11 Performance Monitor Counters (p15, c15, c12, 0)
439  */
440 #define ARM11_PMCCTL_E __BIT(0) /* enable all three counters */
441 #define ARM11_PMCCTL_P __BIT(1) /* reset both Count Registers to zero */
442 #define ARM11_PMCCTL_C __BIT(2) /* reset the Cycle Counter Register to zero */
443 #define ARM11_PMCCTL_D __BIT(3) /* cycle count divide by 64 */
444 #define ARM11_PMCCTL_EC0 __BIT(4) /* Enable Counter Register 0 interrupt */
445 #define ARM11_PMCCTL_EC1 __BIT(5) /* Enable Counter Register 1 interrupt */
446 #define ARM11_PMCCTL_ECC __BIT(6) /* Enable Cycle Counter interrupt */
447 #define ARM11_PMCCTL_SBZa __BIT(7) /* UNP/SBZ */
448 #define ARM11_PMCCTL_CR0 __BIT(8) /* Count Register 0 overflow flag */
449 #define ARM11_PMCCTL_CR1 __BIT(9) /* Count Register 1 overflow flag */
450 #define ARM11_PMCCTL_CCR __BIT(10) /* Cycle Count Register overflow flag */
451 #define ARM11_PMCCTL_X __BIT(11) /* Enable Export of the events to the event bus */
452 #define ARM11_PMCCTL_EVT1 __BITS(19,12) /* source of events for Count Register 1 */
453 #define ARM11_PMCCTL_EVT0 __BITS(27,20) /* source of events for Count Register 0 */
454 #define ARM11_PMCCTL_SBZb __BITS(31,28) /* UNP/SBZ */
455 #define ARM11_PMCCTL_SBZ \
456  (ARM11_PMCCTL_SBZa | ARM11_PMCCTL_SBZb)
457 
458 #define ARM11_PMCEVT_ICACHE_MISS 0 /* Instruction Cache Miss */
459 #define ARM11_PMCEVT_ISTREAM_STALL 1 /* Instruction Stream Stall */
460 #define ARM11_PMCEVT_IUTLB_MISS 2 /* Instruction uTLB Miss */
461 #define ARM11_PMCEVT_DUTLB_MISS 3 /* Data uTLB Miss */
462 #define ARM11_PMCEVT_BRANCH 4 /* Branch Inst. Executed */
463 #define ARM11_PMCEVT_BRANCH_MISS 6 /* Branch mispredicted */
464 #define ARM11_PMCEVT_INST_EXEC 7 /* Instruction Executed */
465 #define ARM11_PMCEVT_DCACHE_ACCESS0 9 /* Data Cache Access */
466 #define ARM11_PMCEVT_DCACHE_ACCESS1 10 /* Data Cache Access */
467 #define ARM11_PMCEVT_DCACHE_MISS 11 /* Data Cache Miss */
468 #define ARM11_PMCEVT_DCACHE_WRITEBACK 12 /* Data Cache Writeback */
469 #define ARM11_PMCEVT_PC_CHANGE 13 /* Software PC change */
470 #define ARM11_PMCEVT_TLB_MISS 15 /* Main TLB Miss */
471 #define ARM11_PMCEVT_DATA_ACCESS 16 /* non-cached data access */
472 #define ARM11_PMCEVT_LSU_STALL 17 /* Load/Store Unit stall */
473 #define ARM11_PMCEVT_WBUF_DRAIN 18 /* Write buffer drained */
474 #define ARM11_PMCEVT_ETMEXTOUT0 32 /* ETMEXTOUT[0] asserted */
475 #define ARM11_PMCEVT_ETMEXTOUT1 33 /* ETMEXTOUT[1] asserted */
476 #define ARM11_PMCEVT_ETMEXTOUT 34 /* ETMEXTOUT[0 & 1] */
477 #define ARM11_PMCEVT_CALL_EXEC 35 /* Procedure call executed */
478 #define ARM11_PMCEVT_RETURN_EXEC 36 /* Return executed */
479 #define ARM11_PMCEVT_RETURN_HIT 37 /* return address predicted */
480 #define ARM11_PMCEVT_RETURN_MISS 38 /* return addr. mispredicted */
481 #define ARM11_PMCEVT_CYCLE 255 /* Increment each cycle */
482 
483 /* Defines for ARM CORTEX performance counters */
484 #define CORTEX_CNTENS_C __BIT(31) /* Enables the cycle counter */
485 #define CORTEX_CNTENC_C __BIT(31) /* Disables the cycle counter */
486 #define CORTEX_CNTOFL_C __BIT(31) /* Cycle counter overflow flag */
487 
488 /* Defines for ARM Cortex A7/A15 L2CTRL */
489 #define L2CTRL_NUMCPU __BITS(25,24) // numcpus - 1
490 #define L2CTRL_ICPRES __BIT(23) // Interrupt Controller is present
491 
492 /* Translation Table Base Register */
493 #define TTBR_C __BIT(0) /* without MPE */
494 #define TTBR_S __BIT(1)
495 #define TTBR_IMP __BIT(2)
496 #define TTBR_RGN_MASK __BITS(4,3)
497 #define TTBR_RGN_NC __SHIFTIN(0, TTBR_RGN_MASK)
498 #define TTBR_RGN_WBWA __SHIFTIN(1, TTBR_RGN_MASK)
499 #define TTBR_RGN_WT __SHIFTIN(2, TTBR_RGN_MASK)
500 #define TTBR_RGN_WBNWA __SHIFTIN(3, TTBR_RGN_MASK)
501 #define TTBR_NOS __BIT(5)
502 #define TTBR_IRGN_MASK (__BIT(6) | __BIT(0))
503 #define TTBR_IRGN_NC 0
504 #define TTBR_IRGN_WBWA __BIT(6)
505 #define TTBR_IRGN_WT __BIT(0)
506 #define TTBR_IRGN_WBNWA (__BIT(0) | __BIT(6))
507 
508 /* Translate Table Base Control Register */
509 #define TTBCR_S_EAE __BIT(31) // Extended Address Extension
510 #define TTBCR_S_PD1 __BIT(5) // Don't use TTBR1
511 #define TTBCR_S_PD0 __BIT(4) // Don't use TTBR0
512 #define TTBCR_S_N __BITS(2,0) // Width of base address in TTB0
513 
514 #define TTBCR_L_EAE __BIT(31) // Extended Address Extension
515 #define TTBCR_L_SH1 __BITS(29,28) // TTBR1 Shareability
516 #define TTBCR_L_ORGN1 __BITS(27,26) // TTBR1 Outer cacheability
517 #define TTBCR_L_IRGN1 __BITS(25,24) // TTBR1 inner cacheability
518 #define TTBCR_L_EPD1 __BIT(23) // Don't use TTBR1
519 #define TTBCR_L_A1 __BIT(22) // ASID is in TTBR1
520 #define TTBCR_L_T1SZ __BITS(18,16) // TTBR1 size offset
521 #define TTBCR_L_SH0 __BITS(13,12) // TTBR0 Shareability
522 #define TTBCR_L_ORGN0 __BITS(11,10) // TTBR0 Outer cacheability
523 #define TTBCR_L_IRGN0 __BITS(9,8) // TTBR0 inner cacheability
524 #define TTBCR_L_EPD0 __BIT(7) // Don't use TTBR0
525 #define TTBCR_L_T0SZ __BITS(2,0) // TTBR0 size offset
526 
527 #define NRRR_ORn(n) __BITS(17+2*(n),16+2*(n)) // Outer Cacheable mappings
528 #define NRRR_IRn(n) __BITS(1+2*(n),0+2*(n)) // Inner Cacheable mappings
529 #define NRRR_NC 0 // non-cacheable
530 #define NRRR_WB_WA 1 // write-back write-allocate
531 #define NRRR_WT 2 // write-through
532 #define NRRR_WB 3 // write-back
533 #define PRRR_NOSn(n) __BITS(24+2*(n))// Memory region is Inner Shareable
534 #define PRRR_NS1 __BIT(19) // Normal Shareable S=1 is Shareable
535 #define PRRR_NS0 __BIT(18) // Normal Shareable S=0 is Shareable
536 #define PRRR_DS1 __BIT(17) // Device Shareable S=1 is Shareable
537 #define PRRR_DS0 __BIT(16) // Device Shareable S=0 is Shareable
538 #define PRRR_TRn(n) __BITS(1+2*(n),0+2*(n))
539 #define PRRR_TR_STRONG 0 // Strongly Ordered
540 #define PRRR_TR_DEVICE 1 // Device
541 #define PRRR_TR_NORMAL 2 // Normal Memory
542 
543 /* ARMv7 MPIDR, Multiprocessor Affinity Register generic format */
544 #define MPIDR_MP __BIT(31) /* 1 = Have MP Extention */
545 #define MPIDR_U __BIT(30) /* 1 = Uni-Processor System */
546 #define MPIDR_MT __BIT(24) /* 1 = SMT(AFF0 is logical) */
547 #define MPIDR_AFF2 __BITS(23,16) /* Affinity Level 2 */
548 #define MPIDR_AFF1 __BITS(15,8) /* Affinity Level 1 */
549 #define MPIDR_AFF0 __BITS(7,0) /* Affinity Level 0 */
550 
551 /* MPIDR implementation of ARM Cortex A9: SMT and AFF2 is not used */
552 #define CORTEXA9_MPIDR_MP MPIDR_MP
553 #define CORTEXA9_MPIDR_U MPIDR_U
554 #define CORTEXA9_MPIDR_CLID __BITS(11,8) /* AFF1 = cluster id */
555 #define CORTEXA9_MPIDR_CPUID __BITS(0,1) /* AFF0 = physical core id */
556 
557 /* MPIDR implementation of Marvell PJ4B-MP: AFF2 is not used */
558 #define PJ4B_MPIDR_MP MPIDR_MP
559 #define PJ4B_MPIDR_U MPIDR_U
560 #define PJ4B_MPIDR_MT MPIDR_MT /* 1 = SMT(AFF0 is logical) */
561 #define PJ4B_MPIDR_CLID __BITS(11,8) /* AFF1 = cluster id */
562 #define PJ4B_MPIDR_CPUID __BITS(0,3) /* AFF0 = core id */
563 
564 /* Defines for ARM Generic Timer */
565 #define CNTCTL_ISTATUS __BIT(2) // Interrupt is pending
566 #define CNTCTL_IMASK __BIT(1) // Mask Interrupt
567 #define CNTCTL_ENABLE __BIT(0) // Timer Enabled
568 
569 #define CNTKCTL_PL0PTEN __BIT(9) /* PL0 Physical Timer Enable */
570 #define CNTKCTL_PL0VTEN __BIT(8) /* PL0 Virtual Timer Enable */
571 #define CNTKCTL_EVNTI __BITS(7,4) /* CNTVCT Event Bit Select */
572 #define CNTKCTL_EVNTDIR __BIT(3) /* CNTVCT Event Dir (1->0) */
573 #define CNTKCTL_EVNTEN __BIT(2) /* CNTVCT Event Enable */
574 #define CNTKCTL_PL0VCTEN __BIT(1) /* PL0 Virtual Counter Enable */
575 #define CNTKCTL_PL0PCTEN __BIT(0) /* PL0 Physical Counter Enable */
576 
577 /* CNCHCTL, Timer PL2 Control register, Virtualization Extensions */
578 #define CNTHCTL_EVNTI __BITS(7,4)
579 #define CNTHCTL_EVNTDIR __BIT(3)
580 #define CNTHCTL_EVNTEN __BIT(2)
581 #define CNTHCTL_PL1PCEN __BIT(1)
582 #define CNTHCTL_PL1PCTEN __BIT(0)
583 
584 #define ARM_A5_TLBDATA_DOM __BITS(62,59)
585 #define ARM_A5_TLBDATA_AP __BITS(58,56)
586 #define ARM_A5_TLBDATA_NS_WALK __BIT(55)
587 #define ARM_A5_TLBDATA_NS_PAGE __BIT(54)
588 #define ARM_A5_TLBDATA_XN __BIT(53)
589 #define ARM_A5_TLBDATA_TEX __BITS(52,50)
590 #define ARM_A5_TLBDATA_B __BIT(49)
591 #define ARM_A5_TLBDATA_C __BIT(48)
592 #define ARM_A5_TLBDATA_S __BIT(47)
593 #define ARM_A5_TLBDATA_ASID __BITS(46,39)
594 #define ARM_A5_TLBDATA_SIZE __BITS(38,37)
595 #define ARM_A5_TLBDATA_SIZE_4KB 0
596 #define ARM_A5_TLBDATA_SIZE_16KB 1
597 #define ARM_A5_TLBDATA_SIZE_1MB 2
598 #define ARM_A5_TLBDATA_SIZE_16MB 3
599 #define ARM_A5_TLBDATA_VA __BITS(36,22)
600 #define ARM_A5_TLBDATA_PA __BITS(21,2)
601 #define ARM_A5_TLBDATA_nG __BIT(1)
602 #define ARM_A5_TLBDATA_VALID __BIT(0)
603 
604 #define ARM_A7_TLBDATA2_S2_LEVEL __BITS(85-64,84-64)
605 #define ARM_A7_TLBDATA2_S1_SIZE __BITS(83-64,82-64)
606 #define ARM_A7_TLBDATA2_S1_SIZE_4KB 0
607 #define ARM_A7_TLBDATA2_S1_SIZE_64KB 1
608 #define ARM_A7_TLBDATA2_S1_SIZE_1MB 2
609 #define ARM_A7_TLBDATA2_S1_SIZE_16MB 3
610 #define ARM_A7_TLBDATA2_DOM __BITS(81-64,78-64)
611 #define ARM_A7_TLBDATA2_IS __BITS(77-64,76-64)
612 #define ARM_A7_TLBDATA2_IS_NC 0
613 #define ARM_A7_TLBDATA2_IS_WB_WA 1
614 #define ARM_A7_TLBDATA2_IS_WT 2
615 #define ARM_A7_TLBDATA2_IS_DSO 3
616 #define ARM_A7_TLBDATA2_S2OVR __BIT(75-64)
617 #define ARM_A7_TLBDATA2_SDO_MT __BITS(74-64,72-64)
618 #define ARM_A7_TLBDATA2_SDO_MT_D 2
619 #define ARM_A7_TLBDATA2_SDO_MT_SO 6
620 #define ARM_A7_TLBDATA2_OS __BITS(75-64,74-64)
621 #define ARM_A7_TLBDATA2_OS_NC 0
622 #define ARM_A7_TLBDATA2_OS_WB_WA 1
623 #define ARM_A7_TLBDATA2_OS_WT 2
624 #define ARM_A7_TLBDATA2_OS_WB 3
625 #define ARM_A7_TLBDATA2_SH __BITS(73-64,72-64)
626 #define ARM_A7_TLBDATA2_SH_NONE 0
627 #define ARM_A7_TLBDATA2_SH_UNUSED 1
628 #define ARM_A7_TLBDATA2_SH_OS 2
629 #define ARM_A7_TLBDATA2_SH_IS 3
630 #define ARM_A7_TLBDATA2_XN2 __BIT(71-64)
631 #define ARM_A7_TLBDATA2_XN1 __BIT(70-64)
632 #define ARM_A7_TLBDATA2_PXN __BIT(69-64)
633 
634 #define ARM_A7_TLBDATA12_PA __BITS(68-32,41-32)
635 
636 #define ARM_A7_TLBDATA1_NS __BIT(40-32)
637 #define ARM_A7_TLBDATA1_HAP __BITS(39-32,38-32)
638 #define ARM_A7_TLBDATA1_AP __BITS(37-32,35-32)
639 #define ARM_A7_TLBDATA1_nG __BIT(34-32)
640 
641 #define ARM_A7_TLBDATA01_ASID __BITS(33,26)
642 
643 #define ARM_A7_TLBDATA0_VMID __BITS(25,18)
644 #define ARM_A7_TLBDATA0_VA __BITS(17,5)
645 #define ARM_A7_TLBDATA0_NS_WALK __BIT(4)
646 #define ARM_A7_TLBDATA0_SIZE __BITS(3,1)
647 #define ARM_A7_TLBDATA0_SIZE_V7_4KB 0
648 #define ARM_A7_TLBDATA0_SIZE_LPAE_4KB 1
649 #define ARM_A7_TLBDATA0_SIZE_V7_64KB 2
650 #define ARM_A7_TLBDATA0_SIZE_LPAE_64KB 3
651 #define ARM_A7_TLBDATA0_SIZE_V7_1MB 4
652 #define ARM_A7_TLBDATA0_SIZE_LPAE_2MB 5
653 #define ARM_A7_TLBDATA0_SIZE_V7_16MB 6
654 #define ARM_A7_TLBDATA0_SIZE_LPAE_1GB 7
655 
656 #define ARM_TLBDATA_VALID __BIT(0)
657 
658 #define ARM_TLBDATAOP_WAY __BIT(31)
659 #define ARM_A5_TLBDATAOP_INDEX __BITS(5,0)
660 #define ARM_A7_TLBDATAOP_INDEX __BITS(6,0)
661 
662 #if !defined(__ASSEMBLER__) && defined(_KERNEL)
663 static inline bool
664 arm_cond_ok_p(uint32_t insn, uint32_t psr)
665 {
666  const uint32_t __cond = __SHIFTOUT(insn, INSN_COND_MASK);
667 
668  bool __ok;
669  const bool __z = (psr & PSR_Z_bit);
670  const bool __n = (psr & PSR_N_bit);
671  const bool __c = (psr & PSR_C_bit);
672  const bool __v = (psr & PSR_V_bit);
673  switch (__cond & ~1) {
674  case INSN_COND_EQ: // Z == 1
675  __ok = __z;
676  break;
677  case INSN_COND_CS: // C == 1
678  __ok = __c;
679  break;
680  case INSN_COND_MI: // N == 1
681  __ok = __n;
682  break;
683  case INSN_COND_VS: // V == 1
684  __ok = __v;
685  break;
686  case INSN_COND_HI: // C == 1 && Z == 0
687  __ok = __c && !__z;
688  break;
689  case INSN_COND_GE: // N == V
690  __ok = __n == __v;
691  break;
692  case INSN_COND_GT: // N == V && Z == 0
693  __ok = __n == __v && !__z;
694  break;
695  default: /* INSN_COND_AL or unconditional */
696  return true;
697  }
698 
699  return (__cond & 1) ? !__ok : __ok;
700 }
701 #endif /* !__ASSEMBLER && _KERNEL */
702 
703 #if !defined(__ASSEMBLER__) && !defined(_RUMPKERNEL)
704 #define ARMREG_READ_INLINE(name, __insnstring) \
705 static inline uint32_t armreg_##name##_read(void) \
706 { \
707  uint32_t __rv; \
708  __asm __volatile("mrc " __insnstring : "=r"(__rv)); \
709  return __rv; \
710 }
711 
712 #define ARMREG_WRITE_INLINE(name, __insnstring) \
713 static inline void armreg_##name##_write(uint32_t __val) \
714 { \
715  __asm __volatile("mcr " __insnstring :: "r"(__val)); \
716 }
717 
718 #define ARMREG_READ_INLINE2(name, __insnstring) \
719 static inline uint32_t armreg_##name##_read(void) \
720 { \
721  uint32_t __rv; \
722  __asm __volatile(".fpu vfp"); \
723  __asm __volatile(__insnstring : "=r"(__rv)); \
724  return __rv; \
725 }
726 
727 #define ARMREG_WRITE_INLINE2(name, __insnstring) \
728 static inline void armreg_##name##_write(uint32_t __val) \
729 { \
730  __asm __volatile(".fpu vfp"); \
731  __asm __volatile(__insnstring :: "r"(__val)); \
732 }
733 
734 #define ARMREG_READ64_INLINE(name, __insnstring) \
735 static inline uint64_t armreg_##name##_read(void) \
736 { \
737  uint64_t __rv; \
738  __asm __volatile("mrrc " __insnstring : "=r"(__rv)); \
739  return __rv; \
740 }
741 
742 #define ARMREG_WRITE64_INLINE(name, __insnstring) \
743 static inline void armreg_##name##_write(uint64_t __val) \
744 { \
745  __asm __volatile("mcrr " __insnstring :: "r"(__val)); \
746 }
747 
748 /* cp10 registers */
749 ARMREG_READ_INLINE2(fpsid, "vmrs\t%0, fpsid") /* VFP System ID */
750 ARMREG_READ_INLINE2(fpscr, "vmrs\t%0, fpscr") /* VFP Status/Control Register */
751 ARMREG_WRITE_INLINE2(fpscr, "vmsr\tfpscr, %0") /* VFP Status/Control Register */
752 ARMREG_READ_INLINE2(mvfr1, "vmrs\t%0, mvfr1") /* Media and VFP Feature Register 1 */
753 ARMREG_READ_INLINE2(mvfr0, "vmrs\t%0, mvfr0") /* Media and VFP Feature Register 0 */
754 ARMREG_READ_INLINE2(fpexc, "vmrs\t%0, fpexc") /* VFP Exception Register */
755 ARMREG_WRITE_INLINE2(fpexc, "vmsr\tfpexc, %0") /* VFP Exception Register */
756 ARMREG_READ_INLINE2(fpinst, "fmrx\t%0, fpinst") /* VFP Exception Instruction */
757 ARMREG_WRITE_INLINE2(fpinst, "fmxr\tfpinst, %0") /* VFP Exception Instruction */
758 ARMREG_READ_INLINE2(fpinst2, "fmrx\t%0, fpinst2") /* VFP Exception Instruction 2 */
759 ARMREG_WRITE_INLINE2(fpinst2, "fmxr\tfpinst2, %0") /* VFP Exception Instruction 2 */
760 
761 /* cp15 c0 registers */
762 ARMREG_READ_INLINE(midr, "p15,0,%0,c0,c0,0") /* Main ID Register */
763 ARMREG_READ_INLINE(ctr, "p15,0,%0,c0,c0,1") /* Cache Type Register */
764 ARMREG_READ_INLINE(tlbtr, "p15,0,%0,c0,c0,3") /* TLB Type Register */
765 ARMREG_READ_INLINE(mpidr, "p15,0,%0,c0,c0,5") /* Multiprocess Affinity Register */
766 ARMREG_READ_INLINE(revidr, "p15,0,%0,c0,c0,6") /* Revision ID Register */
767 ARMREG_READ_INLINE(pfr0, "p15,0,%0,c0,c1,0") /* Processor Feature Register 0 */
768 ARMREG_READ_INLINE(pfr1, "p15,0,%0,c0,c1,1") /* Processor Feature Register 1 */
769 ARMREG_READ_INLINE(mmfr0, "p15,0,%0,c0,c1,4") /* Memory Model Feature Register 0 */
770 ARMREG_READ_INLINE(mmfr1, "p15,0,%0,c0,c1,5") /* Memory Model Feature Register 1 */
771 ARMREG_READ_INLINE(mmfr2, "p15,0,%0,c0,c1,6") /* Memory Model Feature Register 2 */
772 ARMREG_READ_INLINE(mmfr3, "p15,0,%0,c0,c1,7") /* Memory Model Feature Register 3 */
773 ARMREG_READ_INLINE(isar0, "p15,0,%0,c0,c2,0") /* Instruction Set Attribute Register 0 */
774 ARMREG_READ_INLINE(isar1, "p15,0,%0,c0,c2,1") /* Instruction Set Attribute Register 1 */
775 ARMREG_READ_INLINE(isar2, "p15,0,%0,c0,c2,2") /* Instruction Set Attribute Register 2 */
776 ARMREG_READ_INLINE(isar3, "p15,0,%0,c0,c2,3") /* Instruction Set Attribute Register 3 */
777 ARMREG_READ_INLINE(isar4, "p15,0,%0,c0,c2,4") /* Instruction Set Attribute Register 4 */
778 ARMREG_READ_INLINE(isar5, "p15,0,%0,c0,c2,5") /* Instruction Set Attribute Register 5 */
779 ARMREG_READ_INLINE(ccsidr, "p15,1,%0,c0,c0,0") /* Cache Size ID Register */
780 ARMREG_READ_INLINE(clidr, "p15,1,%0,c0,c0,1") /* Cache Level ID Register */
781 ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
782 ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
783 /* cp15 c1 registers */
784 ARMREG_READ_INLINE(sctlr, "p15,0,%0,c1,c0,0") /* System Control Register */
785 ARMREG_WRITE_INLINE(sctlr, "p15,0,%0,c1,c0,0") /* System Control Register */
786 ARMREG_READ_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */
787 ARMREG_WRITE_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */
788 ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */
789 ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */
790 ARMREG_READ_INLINE(scr, "p15,0,%0,c1,c1,0") /* Secure Configuration Register */
791 ARMREG_READ_INLINE(nsacr, "p15,0,%0,c1,c1,2") /* Non-Secure Access Control Register */
792 /* cp15 c2 registers */
793 ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */
794 ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */
795 ARMREG_READ_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */
796 ARMREG_WRITE_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */
797 ARMREG_READ_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
798 ARMREG_WRITE_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
799 /* cp15 c3 registers */
800 ARMREG_READ_INLINE(dacr, "p15,0,%0,c3,c0,0") /* Domain Access Control Register */
801 ARMREG_WRITE_INLINE(dacr, "p15,0,%0,c3,c0,0") /* Domain Access Control Register */
802 /* cp15 c5 registers */
803 ARMREG_READ_INLINE(dfsr, "p15,0,%0,c5,c0,0") /* Data Fault Status Register */
804 ARMREG_READ_INLINE(ifsr, "p15,0,%0,c5,c0,1") /* Instruction Fault Status Register */
805 /* cp15 c6 registers */
806 ARMREG_READ_INLINE(dfar, "p15,0,%0,c6,c0,0") /* Data Fault Address Register */
807 ARMREG_READ_INLINE(ifar, "p15,0,%0,c6,c0,2") /* Instruction Fault Address Register */
808 /* cp15 c7 registers */
809 ARMREG_WRITE_INLINE(icialluis, "p15,0,%0,c7,c1,0") /* Instruction Inv All (IS) */
810 ARMREG_WRITE_INLINE(bpiallis, "p15,0,%0,c7,c1,6") /* Branch Predictor Invalidate All (IS) */
811 ARMREG_READ_INLINE(par, "p15,0,%0,c7,c4,0") /* Physical Address Register */
812 ARMREG_WRITE_INLINE(iciallu, "p15,0,%0,c7,c5,0") /* Instruction Invalidate All */
813 ARMREG_WRITE_INLINE(icimvau, "p15,0,%0,c7,c5,1") /* Instruction Invalidate MVA */
814 ARMREG_WRITE_INLINE(isb, "p15,0,%0,c7,c5,4") /* Instruction Synchronization Barrier */
815 ARMREG_WRITE_INLINE(bpiall, "p15,0,%0,c7,c5,6") /* Branch Predictor Invalidate All */
816 ARMREG_WRITE_INLINE(bpimva, "p15,0,%0,c7,c5,7") /* Branch Predictor invalidate by MVA */
817 ARMREG_WRITE_INLINE(dcimvac, "p15,0,%0,c7,c6,1") /* Data Invalidate MVA to PoC */
818 ARMREG_WRITE_INLINE(dcisw, "p15,0,%0,c7,c6,2") /* Data Invalidate Set/Way */
819 ARMREG_WRITE_INLINE(ats1cpr, "p15,0,%0,c7,c8,0") /* AddrTrans CurState PL1 Read */
820 ARMREG_WRITE_INLINE(ats1cpw, "p15,0,%0,c7,c8,1") /* AddrTrans CurState PL1 Write */
821 ARMREG_WRITE_INLINE(ats1cur, "p15,0,%0,c7,c8,2") /* AddrTrans CurState PL0 Read */
822 ARMREG_WRITE_INLINE(ats1cuw, "p15,0,%0,c7,c8,3") /* AddrTrans CurState PL0 Write */
823 ARMREG_WRITE_INLINE(dccmvac, "p15,0,%0,c7,c10,1") /* Data Clean MVA to PoC */
824 ARMREG_WRITE_INLINE(dccsw, "p15,0,%0,c7,c10,2") /* Data Clean Set/Way */
825 ARMREG_WRITE_INLINE(dsb, "p15,0,%0,c7,c10,4") /* Data Synchronization Barrier */
826 ARMREG_WRITE_INLINE(dmb, "p15,0,%0,c7,c10,5") /* Data Memory Barrier */
827 ARMREG_WRITE_INLINE(dccmvau, "p15,0,%0,c7,c11,1") /* Data Clean MVA to PoU */
828 ARMREG_WRITE_INLINE(dccimvac, "p15,0,%0,c7,c14,1") /* Data Clean&Inv MVA to PoC */
829 ARMREG_WRITE_INLINE(dccisw, "p15,0,%0,c7,c14,2") /* Data Clean&Inv Set/Way */
830 /* cp15 c8 registers */
831 ARMREG_WRITE_INLINE(tlbiallis, "p15,0,%0,c8,c3,0") /* Invalidate entire unified TLB, inner shareable */
832 ARMREG_WRITE_INLINE(tlbimvais, "p15,0,%0,c8,c3,1") /* Invalidate unified TLB by MVA, inner shareable */
833 ARMREG_WRITE_INLINE(tlbiasidis, "p15,0,%0,c8,c3,2") /* Invalidate unified TLB by ASID, inner shareable */
834 ARMREG_WRITE_INLINE(tlbimvaais, "p15,0,%0,c8,c3,3") /* Invalidate unified TLB by MVA, all ASID, inner shareable */
835 ARMREG_WRITE_INLINE(itlbiall, "p15,0,%0,c8,c5,0") /* Invalidate entire instruction TLB */
836 ARMREG_WRITE_INLINE(itlbimva, "p15,0,%0,c8,c5,1") /* Invalidate instruction TLB by MVA */
837 ARMREG_WRITE_INLINE(itlbiasid, "p15,0,%0,c8,c5,2") /* Invalidate instruction TLB by ASID */
838 ARMREG_WRITE_INLINE(dtlbiall, "p15,0,%0,c8,c6,0") /* Invalidate entire data TLB */
839 ARMREG_WRITE_INLINE(dtlbimva, "p15,0,%0,c8,c6,1") /* Invalidate data TLB by MVA */
840 ARMREG_WRITE_INLINE(dtlbiasid, "p15,0,%0,c8,c6,2") /* Invalidate data TLB by ASID */
841 ARMREG_WRITE_INLINE(tlbiall, "p15,0,%0,c8,c7,0") /* Invalidate entire unified TLB */
842 ARMREG_WRITE_INLINE(tlbimva, "p15,0,%0,c8,c7,1") /* Invalidate unified TLB by MVA */
843 ARMREG_WRITE_INLINE(tlbiasid, "p15,0,%0,c8,c7,2") /* Invalidate unified TLB by ASID */
844 ARMREG_WRITE_INLINE(tlbimvaa, "p15,0,%0,c8,c7,3") /* Invalidate unified TLB by MVA, all ASID */
845 /* cp15 c9 registers */
846 ARMREG_READ_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */
847 ARMREG_WRITE_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */
848 ARMREG_READ_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */
849 ARMREG_WRITE_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */
850 ARMREG_READ_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */
851 ARMREG_WRITE_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */
852 ARMREG_READ_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */
853 ARMREG_WRITE_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */
854 ARMREG_READ_INLINE(pmselr, "p15,0,%0,c9,c12,5") /* PMC Event Counter Selection */
855 ARMREG_WRITE_INLINE(pmselr, "p15,0,%0,c9,c12,5") /* PMC Event Counter Selection */
856 ARMREG_READ_INLINE(pmceid0, "p15,0,%0,c9,c12,6") /* PMC Event ID 0 */
857 ARMREG_READ_INLINE(pmceid1, "p15,0,%0,c9,c12,7") /* PMC Event ID 1 */
858 ARMREG_READ_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */
859 ARMREG_WRITE_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */
860 ARMREG_READ_INLINE(pmxevtyper, "p15,0,%0,c9,c13,1") /* PMC Event Type Select */
861 ARMREG_WRITE_INLINE(pmxevtyper, "p15,0,%0,c9,c13,1") /* PMC Event Type Select */
862 ARMREG_READ_INLINE(pmxevcntr, "p15,0,%0,c9,c13,2") /* PMC Event Count */
863 ARMREG_WRITE_INLINE(pmxevcntr, "p15,0,%0,c9,c13,2") /* PMC Event Count */
864 ARMREG_READ_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */
865 ARMREG_WRITE_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */
866 ARMREG_READ_INLINE(pmintenset, "p15,0,%0,c9,c14,1") /* PMC Interrupt Enable Set */
867 ARMREG_WRITE_INLINE(pmintenset, "p15,0,%0,c9,c14,1") /* PMC Interrupt Enable Set */
868 ARMREG_READ_INLINE(pmintenclr, "p15,0,%0,c9,c14,2") /* PMC Interrupt Enable Clear */
869 ARMREG_WRITE_INLINE(pmintenclr, "p15,0,%0,c9,c14,2") /* PMC Interrupt Enable Clear */
870 ARMREG_READ_INLINE(l2ctrl, "p15,1,%0,c9,c0,2") /* A7/A15 L2 Control Register */
871 /* cp10 c10 registers */
872 ARMREG_READ_INLINE(prrr, "p15,0,%0,c10,c2,0") /* Primary Region Remap Register */
873 ARMREG_WRITE_INLINE(prrr, "p15,0,%0,c10,c2,0") /* Primary Region Remap Register */
874 ARMREG_READ_INLINE(nrrr, "p15,0,%0,c10,c2,1") /* Normal Region Remap Register */
875 ARMREG_WRITE_INLINE(nrrr, "p15,0,%0,c10,c2,1") /* Normal Region Remap Register */
876 /* cp15 c13 registers */
877 ARMREG_READ_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */
878 ARMREG_WRITE_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */
879 ARMREG_READ_INLINE(tpidrurw, "p15,0,%0,c13,c0,2") /* User read-write Thread ID Register */
880 ARMREG_WRITE_INLINE(tpidrurw, "p15,0,%0,c13,c0,2") /* User read-write Thread ID Register */
881 ARMREG_READ_INLINE(tpidruro, "p15,0,%0,c13,c0,3") /* User read-only Thread ID Register */
882 ARMREG_WRITE_INLINE(tpidruro, "p15,0,%0,c13,c0,3") /* User read-only Thread ID Register */
883 ARMREG_READ_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */
884 ARMREG_WRITE_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */
885 /* cp14 c12 registers */
886 ARMREG_READ_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */
887 ARMREG_WRITE_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */
888 /* cp15 c14 registers */
889 /* cp15 Global Timer Registers */
890 ARMREG_READ_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */
891 ARMREG_WRITE_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */
892 ARMREG_READ_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */
893 ARMREG_WRITE_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */
894 ARMREG_READ_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */
895 ARMREG_WRITE_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */
896 ARMREG_READ_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */
897 ARMREG_WRITE_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */
898 ARMREG_READ_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */
899 ARMREG_WRITE_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */
900 ARMREG_READ_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */
901 ARMREG_WRITE_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */
902 ARMREG_READ64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */
903 ARMREG_WRITE64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */
904 ARMREG_READ64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */
905 ARMREG_WRITE64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */
906 ARMREG_READ64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */
907 ARMREG_WRITE64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */
908 ARMREG_READ64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */
909 ARMREG_WRITE64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */
910 ARMREG_READ64_INLINE(cntvoff, "p15,4,%Q0,%R0,c14") /* Virtual Offset Register */
911 ARMREG_WRITE64_INLINE(cntvoff, "p15,4,%Q0,%R0,c14") /* Virtual Offset Register */
912 /* cp15 c15 registers */
913 ARMREG_READ_INLINE(cbar, "p15,4,%0,c15,c0,0") /* Configuration Base Address Register */
914 ARMREG_READ_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */
915 ARMREG_WRITE_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */
916 ARMREG_READ_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */
917 ARMREG_WRITE_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */
918 
919 ARMREG_READ_INLINE(tlbdata0, "p15,3,%0,c15,c0,0") /* TLB Data Register 0 (cortex) */
920 ARMREG_READ_INLINE(tlbdata1, "p15,3,%0,c15,c0,1") /* TLB Data Register 1 (cortex) */
921 ARMREG_READ_INLINE(tlbdata2, "p15,3,%0,c15,c0,2") /* TLB Data Register 2 (cortex) */
922 ARMREG_WRITE_INLINE(tlbdataop, "p15,3,%0,c15,c4,2") /* TLB Data Read Operation (cortex) */
923 
924 ARMREG_READ_INLINE(sheeva_xctrl, "p15,1,%0,c15,c1,0") /* Sheeva eXtra Control register */
925 ARMREG_WRITE_INLINE(sheeva_xctrl, "p15,1,%0,c15,c1,0") /* Sheeva eXtra Control register */
926 
927 #if defined(_KERNEL)
928 
929 static inline uint64_t
930 cpu_mpidr_aff_read(void)
931 {
932 
933  return armreg_mpidr_read() & (MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0);
934 }
935 
936 /*
937  * GENERIC TIMER register access
938  */
939 static inline uint32_t
940 gtmr_cntfrq_read(void)
941 {
942 
943  return armreg_cnt_frq_read();
944 }
945 
946 static inline uint32_t
947 gtmr_cntk_ctl_read(void)
948 {
949 
950  return armreg_cntk_ctl_read();
951 }
952 
953 static inline void
954 gtmr_cntk_ctl_write(uint32_t val)
955 {
956 
957  armreg_cntk_ctl_write(val);
958 }
959 
960 static inline uint64_t
961 gtmr_cntpct_read(void)
962 {
963 
964  return armreg_cntp_ct_read();
965 }
966 
967 /*
968  * Counter-timer Virtual Count timer
969  */
970 static inline uint64_t
971 gtmr_cntvct_read(void)
972 {
973 
974  return armreg_cntv_ct_read();
975 }
976 
977 /*
978  * Counter-timer Virtual Timer Control register
979  */
980 static inline uint32_t
981 gtmr_cntv_ctl_read(void)
982 {
983 
984  return armreg_cntv_ctl_read();
985 }
986 
987 static inline void
988 gtmr_cntv_ctl_write(uint32_t val)
989 {
990 
991  armreg_cntv_ctl_write(val);
992 }
993 
994 static inline void
995 gtmr_cntp_ctl_write(uint32_t val)
996 {
997 
998  armreg_cntp_ctl_write(val);
999 }
1000 
1001 
1002 /*
1003  * Counter-timer Virtual Timer TimerValue register
1004  */
1005 static inline uint32_t
1006 gtmr_cntv_tval_read(void)
1007 {
1008 
1009  return armreg_cntv_tval_read();
1010 }
1011 
1012 static inline void
1013 gtmr_cntv_tval_write(uint32_t val)
1014 {
1015 
1016  armreg_cntv_tval_write(val);
1017 }
1018 
1019 
1020 /*
1021  * Counter-timer Virtual Timer CompareValue register
1022  */
1023 static inline uint64_t
1024 gtmr_cntv_cval_read(void)
1025 {
1026 
1027  return armreg_cntv_cval_read();
1028 }
1029 
1030 #endif /* _KERNEL */
1031 #endif /* !__ASSEMBLER && !_RUMPKERNEL */
1032 
1033 #elif defined(__aarch64__)
1034 
1035 #include <aarch64/armreg.h>
1036 
1037 // #endif /* __arm__/__aarch64__ */
1038 
1039 #endif /* _ARM_ARMREG_H */
#define INSN_COND_EQ
Definition: armreg.h:419
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Definition: armreg.h:914
#define ARMREG_WRITE_INLINE2(name, __insnstring)
Definition: armreg.h:727
#define INSN_COND_GE
Definition: armreg.h:429
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Definition: armreg.h:774
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Definition: armreg.h:768
#define INSN_COND_VS
Definition: armreg.h:425
#define ARMREG_WRITE64_INLINE(name, __insnstring)
Definition: armreg.h:742
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Definition: armreg.h:762
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Definition: armreg.h:810
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Definition: armreg.h:903
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Definition: armreg.h:824
#define INSN_COND_GT
Definition: armreg.h:431
#define MPIDR_AFF1
Definition: armreg.h:548
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Definition: armreg.h:858
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Definition: armreg.h:846
#define ARMREG_READ64_INLINE(name, __insnstring)
Definition: armreg.h:734
#define ARMREG_WRITE_INLINE(name, __insnstring)
Definition: armreg.h:712
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Definition: armreg.h:820
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Definition: armreg.h:846
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Definition: armreg.h:762
#define ARMREG_READ_INLINE(name, __insnstring)
Definition: armreg.h:704
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Definition: armreg.h:903
#define PSR_Z_bit
Definition: armreg.h:61
#define MPIDR_AFF0
Definition: armreg.h:549
#define INSN_COND_MASK
Definition: armreg.h:418
#define INSN_COND_CS
Definition: armreg.h:421
#define INSN_COND_HI
Definition: armreg.h:427
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Definition: armreg.h:807
#define PSR_N_bit
Definition: armreg.h:60
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Definition: armreg.h:804
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Definition: armreg.h:801
vmrs t
Definition: armreg.h:750
#define MPIDR_AFF2
Definition: armreg.h:547
#define INSN_COND_MI
Definition: armreg.h:423
#define ARMREG_READ_INLINE2(name, __insnstring)
Definition: armreg.h:718
#define PSR_C_bit
Definition: armreg.h:62
#define PSR_V_bit
Definition: armreg.h:63
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Definition: armreg.h:828

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