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◆ BUG187_SIZE
#define BUG187_SIZE 0x00400000 /* size of BUG PROM */ |
◆ BUG187_START
#define BUG187_START 0xff800000 /* start of BUG PROM */ |
◆ M187_IACK
#define M187_IACK 0xfffe0000 /* interrupt ACK base */ |
◆ M187_ILEVEL
#define M187_ILEVEL 0xfff4203e /* interrupt priority level */ |
◆ M187_IMASK
#define M187_IMASK 0xfff4203f /* interrupt mask level */ |
◆ M187_ISRC
#define M187_ISRC 0x00000000 /* interrupt mask src (NULL) */ |
◆ MVME187_MEM_CTLR
#define MVME187_MEM_CTLR 0xfff43000 /* MEMC040 mem controller */ |
◆ MVME187_SBC_CMMU_D
#define MVME187_SBC_CMMU_D 0xfff7f000 /* Single Board Computer data CMMU */ |
◆ MVME187_SBC_CMMU_I
#define MVME187_SBC_CMMU_I 0xfff77000 /* Single Board Computer code CMMU */ |
◆ MVME187_SRAM_SIZE
#define MVME187_SRAM_SIZE 0x00020000 /* size of sram */ |
◆ MVME187_SRAM_START
#define MVME187_SRAM_START 0xffe00000 /* start of sram used by bug */ |
◆ OBIO187_SIZE
#define OBIO187_SIZE 0x000b0000 /* size of obio space */ |
◆ OBIO187_START
#define OBIO187_START 0xfff40000 /* start of local IO */ |