1 #ifndef MIPS_CPUCOMPONENT_H 2 #define MIPS_CPUCOMPONENT_H 39 #define MIPS_INITIAL_PC ((int32_t) 0xbfc00000) 40 #define MIPS_INITIAL_STACK_POINTER ((int32_t) 0xa0008000 - 256) 44 #define N_MIPS_FCRS 32 45 #define MIPS_FPU_FCIR 0 46 #define MIPS_FPU_FCCR 25 47 #define MIPS_FPU_FCSR 31 48 #define MIPS_FCSR_FCC0_SHIFT 23 49 #define MIPS_FCSR_FCC1_SHIFT 25 51 #define N_MIPS_COPROCS 4 53 #define N_MIPS_GPRS 32 54 #define N_MIPS_FPRS 32 62 #define MIPS_OLDABI_REGISTER_NAMES { \ 63 "zr", "at", "v0", "v1", "a0", "a1", "a2", "a3", \ 64 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \ 65 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \ 66 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" } 67 #define MIPS_REGISTER_NAMES { \ 68 "zr", "at", "v0", "v1", "a0", "a1", "a2", "a3", \ 69 "a4", "a5", "a6", "a7", "t4", "t5", "t6", "t7", \ 70 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \ 71 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" } 73 #define MIPS_GPR_ZERO 0 83 #define MIPS_GPR_T2 10 84 #define MIPS_GPR_T3 11 85 #define MIPS_GPR_T4 12 86 #define MIPS_GPR_T5 13 87 #define MIPS_GPR_T6 14 88 #define MIPS_GPR_T7 15 89 #define MIPS_GPR_S0 16 90 #define MIPS_GPR_S1 17 91 #define MIPS_GPR_S2 18 92 #define MIPS_GPR_S3 19 93 #define MIPS_GPR_S4 20 94 #define MIPS_GPR_S5 21 95 #define MIPS_GPR_S6 22 96 #define MIPS_GPR_S7 23 97 #define MIPS_GPR_T8 24 98 #define MIPS_GPR_T9 25 99 #define MIPS_GPR_K0 26 100 #define MIPS_GPR_K1 27 101 #define MIPS_GPR_GP 28 102 #define MIPS_GPR_SP 29 103 #define MIPS_GPR_FP 30 104 #define MIPS_GPR_RA 31 161 static string GetAttribute(
const string& attributeName);
163 virtual void ResetState();
165 virtual bool PreRunCheckForComponent(
GXemul* gxemul);
167 virtual size_t DisassembleInstruction(uint64_t vaddr,
size_t maxlen,
168 unsigned char *instruction, vector<string>& result);
173 static void RunUnitTests(
int& nSucceeded,
int& nFailures);
176 virtual bool CheckVariableWrite(
StateVariable& var,
const string& oldValue);
178 virtual bool VirtualToPhysical(uint64_t vaddr, uint64_t& paddr,
184 ss.flags(std::ios::hex | std::ios::showbase | std::ios::right);
186 ss << (uint32_t)vaddr;
192 virtual uint64_t PCtoInstructionAddress(uint64_t pc);
194 virtual int FunctionTraceArgumentCount();
195 virtual int64_t FunctionTraceArgument(
int n);
196 virtual bool FunctionTraceReturnImpl(int64_t& retval);
198 virtual int GetDyntransICshift()
const;
201 virtual void ShowRegisters(
GXemul* gxemul,
const vector<string>& arguments)
const;
204 size_t DisassembleInstructionMIPS16(uint64_t vaddr,
205 unsigned char *instruction, vector<string>& result);
207 bool Is32Bit()
const;
243 #endif // MIPS_CPUCOMPONENT_H
struct arm_instr_call * ic
A dyntrans instruction call.
A Component representing a MIPS processor.
A base-class for processors Component implementations that use dynamic translation.
virtual void(*)(CPUDyntransComponent *, DyntransIC *) GetDyntransToBeTranslated()
StateVariables make up the persistent state of Component objects.
#define DECLARE_DYNTRANS_INSTR(name)
virtual string VirtualAddressAsString(uint64_t vaddr)
Format a virtual address as a displayable string.