bus_pci.h Source File

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bus_pci.h
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1 #ifndef BUS_PCI_H
2 #define BUS_PCI_H
3 
4 /*
5  * Copyright (C) 2004-2010 Anders Gavare. All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright
11  * notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  * notice, this list of conditions and the following disclaimer in the
14  * documentation and/or other materials provided with the distribution.
15  * 3. The name of the author may not be used to endorse or promote products
16  * derived from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  *
30  *
31  * PCI bus.
32  */
33 
34 #include "misc.h"
35 
36 #include "thirdparty/pcireg.h"
37 
38 struct machine;
39 struct memory;
40 
41 struct pci_device;
42 
43 
44 #ifndef BUS_PCI_C
45 
46 struct pci_data;
47 
48 #else
49 
50 struct pci_data {
51  /*
52  * IRQ paths:
53  *
54  * irq_path Path of the controller itself.
55  * irq_path_isa Path base of ISA interrupts.
56  * irq_path_pci Path base of PCI interrupts.
57  */
58  char *irq_path;
59  char *irq_path_isa;
60  char *irq_path_pci;
61 
62  /*
63  * Default I/O port, memory, and irq bases for PCI and legacy ISA
64  * devices, and the base address for actual (emulated) devices:
65  *
66  * pci_portbase etc are what is stored in the device configuration
67  * registers. This address + pci_actual_{io,mem}_offset is where the
68  * emulated device should be registered.
69  */
70  uint64_t pci_actual_io_offset;
71  uint64_t pci_actual_mem_offset;
72 
73  uint64_t pci_portbase;
74  uint64_t pci_membase;
75 
76  uint64_t isa_portbase;
77  uint64_t isa_membase;
78 
79  /* Current base when allocating space for PCI devices: */
80  uint64_t cur_pci_portbase;
81  uint64_t cur_pci_membase;
82 
83  /* Current register access: */
84  int cur_bus, cur_device, cur_func, cur_reg;
85  int last_was_write_ffffffff;
86 
87  struct pci_device *first_device;
88 };
89 
90 #define PCI_CFG_MEM_SIZE 0x100
91 
92 struct pci_device {
93  /* Pointer to the next PCI device on this bus: */
94  struct pci_device *next;
95 
96  /* Pointer back to the bus this device is connected to: */
97  struct pci_data *pcibus;
98 
99  /* Short device name, and bus/device/function value: */
100  char *name;
101  int bus, device, function;
102 
103  /* Configuration memory: */
104  unsigned char cfg_mem[PCI_CFG_MEM_SIZE];
105  unsigned char cfg_mem_size[PCI_CFG_MEM_SIZE];
106 
107  /* Used when setting up the configuration registers: */
108  int cur_mapreg_offset;
109 
110  /* Function to handle device-specific cfg register writes: */
111  int (*cfg_reg_write)(struct pci_device *pd,
112  int reg, uint32_t value);
113  void *extra;
114 };
115 
116 #define PCIINIT(name) void pciinit_ ## name(struct machine *machine, \
117  struct memory *mem, struct pci_device *pd)
118 
119 /*
120  * Store little-endian config data in the pci_data struct's cfg_mem[]
121  * or cfg_mem_size[], respectively.
122  */
123 #define PCI_SET_DATA(ofs,value) { \
124  pd->cfg_mem[(ofs)] = (value) & 255; \
125  pd->cfg_mem[(ofs) + 1] = ((value) >> 8) & 255; \
126  pd->cfg_mem[(ofs) + 2] = ((value) >> 16) & 255; \
127  pd->cfg_mem[(ofs) + 3] = ((value) >> 24) & 255; \
128  }
129 #define PCI_SET_DATA_SIZE(ofs,value) { \
130  pd->cfg_mem_size[(ofs)] = (value) & 255; \
131  pd->cfg_mem_size[(ofs) + 1] = ((value) >> 8) & 255; \
132  pd->cfg_mem_size[(ofs) + 2] = ((value) >> 16) & 255; \
133  pd->cfg_mem_size[(ofs) + 3] = ((value) >> 24) & 255; \
134  }
135 
136 #endif
137 
138 #define BUS_PCI_ADDR 0xcf8
139 #define BUS_PCI_DATA 0xcfc
140 
141 
142 /*
143  * bus_pci.c:
144  */
145 
146 /* Run-time access: */
147 void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg);
148 void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data,
149  int bus, int device, int function, int reg);
150 void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data,
151  uint64_t *data, int len, int writeflag);
152 
153 /* Initialization: */
154 struct pci_data *bus_pci_init(struct machine *machine, const char *irq_path,
155  uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset,
156  uint64_t pci_portbase, uint64_t pci_membase, const char *pci_irqbase,
157  uint64_t isa_portbase, uint64_t isa_membase, const char *isa_irqbase);
158 
159 /* Add a PCI device to a PCI bus: */
160 void bus_pci_add(struct machine *machine, struct pci_data *pci_data,
161  struct memory *mem, int bus, int device, int function,
162  const char *name);
163 
164 
165 #endif /* BUS_PCI_H */
void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data, int bus, int device, int function, int reg)
Definition: bus_pci.cc:196
void bus_pci_add(struct machine *machine, struct pci_data *pci_data, struct memory *mem, int bus, int device, int function, const char *name)
Definition: bus_pci.cc:216
#define reg(x)
u_short data
Definition: siireg.h:79
void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data, uint64_t *data, int len, int writeflag)
Definition: bus_pci.cc:95
void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg)
Definition: bus_pci.cc:76
Definition: cpu.h:326
struct pci_data * bus_pci_init(struct machine *machine, const char *irq_path, uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset, uint64_t pci_portbase, uint64_t pci_membase, const char *pci_irqbase, uint64_t isa_portbase, uint64_t isa_membase, const char *isa_irqbase)
Definition: bus_pci.cc:355
Definition: memory.h:75
vmrs t
Definition: armreg.h:750

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