sccreg.h Source File

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sccreg.h
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1 #ifndef SCCREG_H
2 #define SCCREG_H
3 
4 /* $NetBSD: sccreg.h,v 1.6 1999/04/24 08:01:07 simonb Exp $ */
5 
6 /*-
7  * Copyright (c) 1992, 1993
8  * The Regents of the University of California. All rights reserved.
9  *
10  * This code is derived from software contributed to Berkeley by
11  * Ralph Campbell and Rick Macklem.
12  *
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions
15  * are met:
16  * 1. Redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer.
18  * 2. Redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution.
21  * 3. All advertising materials mentioning features or use of this software
22  * must display the following acknowledgement:
23  * This product includes software developed by the University of
24  * California, Berkeley and its contributors.
25  * 4. Neither the name of the University nor the names of its contributors
26  * may be used to endorse or promote products derived from this software
27  * without specific prior written permission.
28  *
29  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32  * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39  * SUCH DAMAGE.
40  *
41  * @(#)sccreg.h 8.1 (Berkeley) 6/10/93
42  */
43 
44 /*
45  * Mach Operating System
46  * Copyright (c) 1991,1990,1989 Carnegie Mellon University
47  * All Rights Reserved.
48  *
49  * Permission to use, copy, modify and distribute this software and its
50  * documentation is hereby granted, provided that both the copyright
51  * notice and this permission notice appear in all copies of the
52  * software, derivative works or modified versions, and any portions
53  * thereof, and that both notices appear in supporting documentation.
54  *
55  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
56  * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
57  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
58  *
59  * Carnegie Mellon requests users of this software to return to
60  *
61  * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
62  * School of Computer Science
63  * Carnegie Mellon University
64  * Pittsburgh PA 15213-3890
65  *
66  * any improvements or extensions that they make and grant Carnegie Mellon
67  * the rights to redistribute these changes.
68  */
69 /*
70  * Definitions for Intel 82530 serial communications chip.
71  * Each chip is a dual uart with the A channels used for the keyboard and
72  * mouse with the B channel(s) for comm ports with modem control. Since
73  * some registers are used for the other channel, the following macros
74  * are used to access the register ports.
75  */
76 typedef struct scc_regmap {
77  /* Channel B is first, then A */
78  struct {
79  char scc_pad0;
80  volatile u_char scc_command; /* reg select */
81  char scc_pad1[3];
82  volatile u_char scc_data; /* Rx/Tx buffer */
83  char scc_pad3[2];
84  } scc_channel[2];
85 } scc_regmap_t;
86 
87 #define SCC_CHANNEL_A 1
88 #define SCC_CHANNEL_B 0
89 
90 #define SCC_INIT_REG(scc,chan) { \
91  char tmp; \
92  tmp = (scc)->scc_channel[(chan)].scc_command; \
93  tmp = (scc)->scc_channel[(chan)].scc_command; \
94  }
95 
96 #define SCC_READ_REG(scc,chan,reg,val) { \
97  (scc)->scc_channel[(chan)].scc_command = (reg); \
98  (val) = (scc)->scc_channel[(chan)].scc_command; \
99  }
100 
101 #define SCC_READ_REG_ZERO(scc,chan,val) { \
102  (val) = (scc)->scc_channel[(chan)].scc_command; \
103  }
104 
105 #define SCC_WRITE_REG(scc,chan,reg,val) { \
106  (scc)->scc_channel[(chan)].scc_command = (reg); \
107  (scc)->scc_channel[(chan)].scc_command = (val); \
108  }
109 
110 #define SCC_WRITE_REG_ZERO(scc,chan,val) { \
111  (scc)->scc_channel[(chan)].scc_command = (val); \
112  }
113 
114 #define SCC_READ_DATA(scc,chan,val) { \
115  (val) = (scc)->scc_channel[(chan)].scc_data; \
116  }
117 
118 #define SCC_WRITE_DATA(scc,chan,val) { \
119  (scc)->scc_channel[(chan)].scc_data = (val); \
120  }
121 
122 #define SCC_RR0 0 /* status register */
123 #define SCC_RR1 1 /* special receive conditions */
124 #define SCC_RR2 2 /* (modified) interrupt vector */
125 #define SCC_RR3 3 /* interrupts pending (cha A only) */
126 #define SCC_RR8 8 /* recv buffer (alias for data) */
127 #define SCC_RR10 10 /* sdlc status */
128 #define SCC_RR12 12 /* BRG constant, low part */
129 #define SCC_RR13 13 /* BRG constant, high part */
130 #define SCC_RR15 15 /* interrupts currently enabled */
131 
132 #define SCC_WR0 0 /* reg select, and commands */
133 #define SCC_WR1 1 /* interrupt and DMA enables */
134 #define SCC_WR2 2 /* interrupt vector */
135 #define SCC_WR3 3 /* receiver params and enables */
136 #define SCC_WR4 4 /* clock/char/parity params */
137 #define SCC_WR5 5 /* xmit params and enables */
138 #define SCC_WR6 6 /* synchr SYNCH/address */
139 #define SCC_WR7 7 /* synchr SYNCH/flag */
140 #define SCC_WR8 8 /* xmit buffer (alias for data) */
141 #define SCC_WR9 9 /* vectoring and resets */
142 #define SCC_WR10 10 /* synchr params */
143 #define SCC_WR11 11 /* clocking definitions */
144 #define SCC_WR12 12 /* BRG constant, low part */
145 #define SCC_WR13 13 /* BRG constant, high part */
146 #define SCC_WR14 14 /* BRG enables and commands */
147 #define SCC_WR15 15 /* interrupt enables */
148 
149 /*
150  * Read registers defines
151  */
152 #define SCC_RR0_BREAK 0x80 /* break detected (rings twice), or */
153 #define SCC_RR0_ABORT 0x80 /* abort (synchr) */
154 #define SCC_RR0_TX_UNDERRUN 0x40 /* xmit buffer empty/end of message */
155 #define SCC_RR0_CTS 0x20 /* clear-to-send pin active (sampled
156  only on intr and after RESI cmd */
157 #define SCC_RR0_SYNCH 0x10 /* SYNCH found/still hunting */
158 #define SCC_RR0_DCD 0x08 /* carrier-detect (same as CTS) */
159 #define SCC_RR0_TX_EMPTY 0x04 /* xmit buffer empty */
160 #define SCC_RR0_ZERO_COUNT 0x02 /* ? */
161 #define SCC_RR0_RX_AVAIL 0x01 /* recv fifo not empty */
162 
163 #define SCC_RR1_EOF 0x80 /* end-of-frame, SDLC mode */
164 #define SCC_RR1_CRC_ERR 0x40 /* incorrect CRC or.. */
165 #define SCC_RR1_FRAME_ERR 0x40 /* ..bad frame */
166 #define SCC_RR1_RX_OVERRUN 0x20 /* rcv fifo overflow */
167 #define SCC_RR1_PARITY_ERR 0x10 /* incorrect parity in data */
168 #define SCC_RR1_RESIDUE0 0x08
169 #define SCC_RR1_RESIDUE1 0x04
170 #define SCC_RR1_RESIDUE2 0x02
171 #define SCC_RR1_ALL_SENT 0x01
172 
173 /* RR2 contains the interrupt vector unmodified (channel A) or
174  modified as follows (channel B, if vector-include-status) */
175 
176 #define SCC_RR2_STATUS(val) ((val)&0xf)
177 
178 #define SCC_RR2_B_XMIT_DONE 0x0
179 #define SCC_RR2_B_EXT_STATUS 0x2
180 #define SCC_RR2_B_RECV_DONE 0x4
181 #define SCC_RR2_B_RECV_SPECIAL 0x6
182 #define SCC_RR2_A_XMIT_DONE 0x8
183 #define SCC_RR2_A_EXT_STATUS 0xa
184 #define SCC_RR2_A_RECV_DONE 0xc
185 #define SCC_RR2_A_RECV_SPECIAL 0xe
186 
187 /* Interrupts pending, to be read from channel A only (B raz) */
188 #define SCC_RR3_zero 0xc0
189 #define SCC_RR3_RX_IP_A 0x20
190 #define SCC_RR3_TX_IP_A 0x10
191 #define SCC_RR3_EXT_IP_A 0x08
192 #define SCC_RR3_RX_IP_B 0x04
193 #define SCC_RR3_TX_IP_B 0x02
194 #define SCC_RR3_EXT_IP_B 0x01
195 
196 /* RR8 is the receive data buffer, a 3 deep FIFO */
197 #define SCC_RECV_BUFFER SCC_RR8
198 #define SCC_RECV_FIFO_DEEP 3
199 
200 #define SCC_RR10_1CLKS 0x80
201 #define SCC_RR10_2CLKS 0x40
202 #define SCC_RR10_zero 0x2d
203 #define SCC_RR10_LOOP_SND 0x10
204 #define SCC_RR10_ON_LOOP 0x02
205 
206 /* RR12/RR13 hold the timing base, upper byte in RR13 */
207 
208 #define SCC_GET_TIMING_BASE(scc,chan,val) { \
209  char tmp; \
210  SCC_READ_REG(scc,chan,SCC_RR12,val);\
211  SCC_READ_REG(scc,chan,SCC_RR13,tmp);\
212  (val) = ((val)<<8)|(tmp&0xff);\
213  }
214 
215 #define SCC_RR15_BREAK_IE 0x80
216 #define SCC_RR15_TX_UNDERRUN_IE 0x40
217 #define SCC_RR15_CTS_IE 0x20
218 #define SCC_RR15_SYNCH_IE 0x10
219 #define SCC_RR15_DCD_IE 0x08
220 #define SCC_RR15_zero 0x05
221 #define SCC_RR15_ZERO_COUNT_IE 0x02
222 
223 /*
224  * Write registers defines
225  */
226 /* WR0 is used for commands too */
227 #define SCC_RESET_TXURUN_LATCH 0xc0
228 #define SCC_RESET_TX_CRC 0x80
229 #define SCC_RESET_RX_CRC 0x40
230 #define SCC_RESET_HIGHEST_IUS 0x38 /* channel A only */
231 #define SCC_RESET_ERROR 0x30
232 #define SCC_RESET_TX_IP 0x28
233 #define SCC_IE_NEXT_CHAR 0x20
234 #define SCC_SEND_SDLC_ABORT 0x18
235 #define SCC_RESET_EXT_IP 0x10
236 
237 #define SCC_WR1_DMA_ENABLE 0x80 /* dma control */
238 #define SCC_WR1_DMA_MODE 0x40 /* drive ~req for DMA controller */
239 #define SCC_WR1_DMA_RECV_DATA 0x20 /* from wire to host memory */
240  /* interrupt enable/conditions */
241 #define SCC_WR1_RXI_SPECIAL_O 0x18 /* on special only */
242 #define SCC_WR1_RXI_ALL_CHAR 0x10 /* on each char, or special */
243 #define SCC_WR1_RXI_FIRST_CHAR 0x08 /* on first char, or special */
244 #define SCC_WR1_RXI_DISABLE 0x00 /* never on recv */
245 #define SCC_WR1_PARITY_IE 0x04 /* on parity errors */
246 #define SCC_WR1_TX_IE 0x02
247 #define SCC_WR1_EXT_IE 0x01
248 
249 /* WR2 is common and contains the interrupt vector (high nibble) */
250 
251 #define SCC_WR3_RX_8_BITS 0xc0
252 #define SCC_WR3_RX_6_BITS 0x80
253 #define SCC_WR3_RX_7_BITS 0x40
254 #define SCC_WR3_RX_5_BITS 0x00
255 #define SCC_WR3_AUTO_ENABLE 0x20
256 #define SCC_WR3_HUNT_MODE 0x10
257 #define SCC_WR3_RX_CRC_ENABLE 0x08
258 #define SCC_WR3_SDLC_SRCH 0x04
259 #define SCC_WR3_INHIBIT_SYNCH 0x02
260 #define SCC_WR3_RX_ENABLE 0x01
261 
262 /* Should be re-written after reset */
263 #define SCC_WR4_CLK_x64 0xc0 /* clock divide factor */
264 #define SCC_WR4_CLK_x32 0x80
265 #define SCC_WR4_CLK_x16 0x40
266 #define SCC_WR4_CLK_x1 0x00
267 #define SCC_WR4_EXT_SYNCH_MODE 0x30 /* synch modes */
268 #define SCC_WR4_SDLC_MODE 0x20
269 #define SCC_WR4_16BIT_SYNCH 0x10
270 #define SCC_WR4_8BIT_SYNCH 0x00
271 #define SCC_WR4_2_STOP 0x0c /* asynch modes */
272 #define SCC_WR4_1_5_STOP 0x08
273 #define SCC_WR4_1_STOP 0x04
274 #define SCC_WR4_SYNCH_MODE 0x00
275 #define SCC_WR4_EVEN_PARITY 0x02
276 #define SCC_WR4_PARITY_ENABLE 0x01
277 
278 #define SCC_WR5_DTR 0x80 /* drive DTR pin */
279 #define SCC_WR5_TX_8_BITS 0x60
280 #define SCC_WR5_TX_6_BITS 0x40
281 #define SCC_WR5_TX_7_BITS 0x20
282 #define SCC_WR5_TX_5_BITS 0x00
283 #define SCC_WR5_SEND_BREAK 0x10
284 #define SCC_WR5_TX_ENABLE 0x08
285 #define SCC_WR5_CRC_16 0x04 /* CRC if non zero, .. */
286 #define SCC_WR5_SDLC 0x00 /* ..SDLC otherwise */
287 #define SCC_WR5_RTS 0x02 /* drive RTS pin */
288 #define SCC_WR5_TX_CRC_ENABLE 0x01
289 
290 /* Registers WR6 and WR7 are for synch modes data, with among other things: */
291 
292 #define SCC_WR6_BISYNCH_12 0x0f
293 #define SCC_WR6_SDLC_RANGE_MASK 0x0f
294 #define SCC_WR7_SDLC_FLAG 0x7e
295 
296 /* WR8 is the transmit data buffer (no FIFO) */
297 #define SCC_XMT_BUFFER SCC_WR8
298 
299 #define SCC_WR9_HW_RESET 0xc0 /* force hardware reset */
300 #define SCC_WR9_RESET_CHA_A 0x80
301 #define SCC_WR9_RESET_CHA_B 0x40
302 #define SCC_WR9_NON_VECTORED 0x20 /* mbz for Zilog chip */
303 #define SCC_WR9_STATUS_HIGH 0x10
304 #define SCC_WR9_MASTER_IE 0x08
305 #define SCC_WR9_DLC 0x04 /* disable-lower-chain */
306 #define SCC_WR9_NV 0x02 /* no vector */
307 #define SCC_WR9_VIS 0x01 /* vector-includes-status */
308 
309 #define SCC_WR10_CRC_PRESET 0x80
310 #define SCC_WR10_FM0 0x60
311 #define SCC_WR10_FM1 0x40
312 #define SCC_WR10_NRZI 0x20
313 #define SCC_WR10_NRZ 0x00
314 #define SCC_WR10_ACTIVE_ON_POLL 0x10
315 #define SCC_WR10_MARK_IDLE 0x08 /* flag if zero */
316 #define SCC_WR10_ABORT_ON_URUN 0x04 /* flag if zero */
317 #define SCC_WR10_LOOP_MODE 0x02
318 #define SCC_WR10_6BIT_SYNCH 0x01
319 #define SCC_WR10_8BIT_SYNCH 0x00
320 
321 #define SCC_WR11_RTxC_XTAL 0x80 /* RTxC pin is input (ext oscill) */
322 #define SCC_WR11_RCLK_DPLL 0x60 /* clock received data on dpll */
323 #define SCC_WR11_RCLK_BAUDR 0x40 /* .. on BRG */
324 #define SCC_WR11_RCLK_TRc_PIN 0x20 /* .. on TRxC pin */
325 #define SCC_WR11_RCLK_RTc_PIN 0x00 /* .. on RTxC pin */
326 #define SCC_WR11_XTLK_DPLL 0x18
327 #define SCC_WR11_XTLK_BAUDR 0x10
328 #define SCC_WR11_XTLK_TRc_PIN 0x08
329 #define SCC_WR11_XTLK_RTc_PIN 0x00
330 #define SCC_WR11_TRc_OUT 0x04 /* drive TRxC pin as output from..*/
331 #define SCC_WR11_TRcOUT_DPLL 0x03 /* .. the dpll */
332 #define SCC_WR11_TRcOUT_BAUDR 0x02 /* .. the BRG */
333 #define SCC_WR11_TRcOUT_XMTCLK 0x01 /* .. the xmit clock */
334 #define SCC_WR11_TRcOUT_XTAL 0x00 /* .. the external oscillator */
335 
336 /* WR12/WR13 are for timing base preset */
337 #define SCC_SET_TIMING_BASE(scc,chan,val) { \
338  SCC_WRITE_REG(scc,chan,SCC_RR12,val);\
339  SCC_WRITE_REG(scc,chan,SCC_RR13,(val)>>8);\
340  }
341 
342 /* More commands in this register */
343 #define SCC_WR14_NRZI_MODE 0xe0 /* synch modulations */
344 #define SCC_WR14_FM_MODE 0xc0
345 #define SCC_WR14_RTc_SOURCE 0xa0 /* clock is from pin .. */
346 #define SCC_WR14_BAUDR_SOURCE 0x80 /* .. or internal BRG */
347 #define SCC_WR14_DISABLE_DPLL 0x60
348 #define SCC_WR14_RESET_CLKMISS 0x40
349 #define SCC_WR14_SEARCH_MODE 0x20
350 /* ..and more bitsy */
351 #define SCC_WR14_LOCAL_LOOPB 0x10
352 #define SCC_WR14_AUTO_ECHO 0x08
353 #define SCC_WR14_DTR_REQUEST 0x04
354 #define SCC_WR14_BAUDR_SRC 0x02
355 #define SCC_WR14_BAUDR_ENABLE 0x01
356 
357 #define SCC_WR15_BREAK_IE 0x80
358 #define SCC_WR15_TX_UNDERRUN_IE 0x40
359 #define SCC_WR15_CTS_IE 0x20
360 #define SCC_WR15_SYNCHUNT_IE 0x10
361 #define SCC_WR15_DCD_IE 0x08
362 #define SCC_WR15_zero 0x05
363 #define SCC_WR15_ZERO_COUNT_IE 0x02
364 
365 /* bits in dm lsr, copied from dmreg.h */
366 #define DML_DSR 0000400 /* data set ready, not a real DM bit */
367 #define DML_RNG 0000200 /* ring */
368 #define DML_CAR 0000100 /* carrier detect */
369 #define DML_CTS 0000040 /* clear to send */
370 #define DML_SR 0000020 /* secondary receive */
371 #define DML_ST 0000010 /* secondary transmit */
372 #define DML_RTS 0000004 /* request to send */
373 #define DML_DTR 0000002 /* data terminal ready */
374 #define DML_LE 0000001 /* line enable */
375 
376 /*
377  * Minor device numbers for scc. Weird because B channel comes
378  * first and the A channels are wired for keyboard/mouse and the
379  * B channels for the comm port(s).
380  */
381 #define SCCCOMM2_PORT 0x0
382 #define SCCMOUSE_PORT 0x1
383 #define SCCCOMM3_PORT 0x2
384 #define SCCKBD_PORT 0x3
385 
386 #endif /* SCCREG_H */
char scc_pad0
Definition: sccreg.h:79
volatile u_char scc_command
Definition: sccreg.h:80
struct scc_regmap scc_regmap_t
volatile u_char scc_data
Definition: sccreg.h:82
char scc_pad3[2]
Definition: sccreg.h:83
char scc_pad1[3]
Definition: sccreg.h:81
struct scc_regmap::@18 scc_channel[2]

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