67 #define SH4_REG_BASE 0xff000000 68 #define SH4_TICK_SHIFT 14 69 #define N_SH4_TIMERS 3 72 #define N_PCIC_REGS (0x224 / sizeof(uint32_t)) 73 #define N_PCIC_IRQS 16 74 #define PCIC_REG(addr) ((addr - SH4_PCIC) / sizeof(uint32_t)) 75 #define PCI_VENDOR_HITACHI 0x1054 76 #define PCI_PRODUCT_HITACHI_SH7751 0x3505 77 #define PCI_PRODUCT_HITACHI_SH7751R 0x350e 79 #define SCIF_TX_FIFO_SIZE 16 80 #define SCIF_DELAYED_TX_VALUE 2 88 #define SH4_CPG_FRQCR 0xffc00000 89 #define SH4_CPG_STBCR 0xffc00004 90 #define SH4_CPG_WTCNT 0xffc00008 91 #define SH4_CPG_WTCSR 0xffc0000c 92 #define SH4_CPG_STBCR2 0xffc00010 176 #define SH4_PSEUDO_TIMER_HZ 110.0 188 static void sh4_timer_tick(
struct timer *
t,
void *
extra)
196 fatal(
"sh4: RTCSR_CMIE | RTCSR_OVIE: TODO\n");
203 int32_t old = d->
tcnt[i];
216 if ((int32_t)d->
tcnt[i] < 0 && old >= 0) {
231 if ((int32_t)d->
tcnt[i] < 0)
243 static void sh4_pcic_interrupt_deassert(
struct interrupt *interrupt)
250 static void scif_reassert_interrupts(
struct sh4_data *d)
305 scif_reassert_interrupts(d);
326 uint32_t sar = cpu->
cd.
sh.
dmac_sar[channel] & 0x1fffffff;
327 uint32_t dar = cpu->
cd.
sh.
dmac_dar[channel] & 0x1fffffff;
328 uint32_t count = cpu->
cd.
sh.
dmac_tcr[channel] & 0x1fffffff;
330 int transmit_size = 1;
331 int src_delta = 0, dst_delta = 0;
332 int cause_interrupt = chcr &
CHCR_IE;
352 default:
fatal(
"Unimplemented transmit size?! CHCR[%i] = 0x%08x\n",
361 default:
fatal(
"Unimplemented destination delta?! CHCR[%i] = 0x%08x\n",
370 default:
fatal(
"Unimplemented source delta?! CHCR[%i] = 0x%08x\n",
375 src_delta *= transmit_size;
376 dst_delta *= transmit_size;
379 fatal(
"|SH4 DMA transfer, channel %i\n", channel);
380 fatal(
"|Source addr: 0x%08x (delta %i)\n", (
int) sar, src_delta);
381 fatal(
"|Destination addr: 0x%08x (delta %i)\n", (
int) dar, dst_delta);
382 fatal(
"|Count: 0x%08x\n", (
int) count);
383 fatal(
"|Transmit size: 0x%08x\n", (
int) transmit_size);
384 fatal(
"|Interrupt: %s\n", cause_interrupt?
"yes" :
"no");
402 default:
fatal(
"Unimplemented SH4 RS DMAC: 0x%08x\n",
403 (
int) (chcr & CHCR_RS));
407 if (cause_interrupt) {
408 fatal(
"TODO: sh4 dmac interrupt!\n");
429 int writeflag = cmd & 0x40? 0 : 1;
430 int address_transfer;
435 fatal(
"SCI cmd bit 7 not set? TODO\n");
439 if ((cmd & 0x30) == 0x20)
440 address_transfer = 1;
441 else if ((cmd & 0x30) == 0x10)
442 address_transfer = 0;
444 fatal(
"SCI: Neither data nor address transfer? TODO\n");
448 if (address_transfer)
458 debug(
"[ SCI: read addr=%x data=%x ]\n",
465 if (data_byte & 0x80)
469 if (writeflag && !address_transfer) {
471 uint8_t data_byte = cmd & 0x0f;
473 debug(
"[ SCI: write addr=%x data=%x ]\n",
489 static uint8_t sh4_sci_access(
struct sh4_data *d,
struct cpu *cpu,
490 int writeflag, uint8_t input)
546 uint64_t idata = 0, odata = 0;
550 int safe_to_invalidate = 0;
553 safe_to_invalidate = 1;
569 if (safe_to_invalidate)
592 uint64_t idata = 0, odata = 0;
595 if (relative_addr & 0x800000) {
596 fatal(
"sh4_itlb_da1: TODO: da2 area\n");
602 int safe_to_invalidate = 0;
604 safe_to_invalidate = 1;
615 if (safe_to_invalidate)
634 uint64_t idata = 0, odata = 0;
640 int safe_to_invalidate = 0;
641 uint32_t vaddr_to_invalidate = 0;
647 uint32_t mask = 0xfffff000;
670 if ((hi & mask) != (idata & mask))
673 if ((lo & SH4_PTEL_SZ_MASK) ==
675 safe_to_invalidate = 1;
676 vaddr_to_invalidate = hi & mask;
680 (cpu->
cd.
sh.
pteh & SH4_PTEH_ASID_MASK))
711 safe_to_invalidate = 1;
712 vaddr_to_invalidate =
728 if (safe_to_invalidate)
752 uint64_t idata = 0, odata = 0;
755 if (relative_addr & 0x800000) {
756 fatal(
"sh4_utlb_da1: TODO: da2 area\n");
762 int safe_to_invalidate = 0;
764 safe_to_invalidate = 1;
775 if (safe_to_invalidate)
795 uint64_t idata = 0, odata = 0;
810 switch (relative_addr) {
814 fatal(
"[ sh4_pcic: TODO: Write to SH4_PCICONF0? ]\n");
825 fatal(
"sh4_pcic: TODO: PCICONF0 read for" 826 " unimplemented CPU type?\n");
846 if (writeflag ==
MEM_WRITE && idata != 0xac000000) {
847 fatal(
"sh4_pcic: SH4_PCICONF5 unknown value" 848 " 0x%" PRIx32
"\n", (uint32_t) idata);
855 if (writeflag ==
MEM_WRITE && idata != 0x8c000000) {
856 fatal(
"sh4_pcic: SH4_PCICONF6 unknown value" 857 " 0x%" PRIx32
"\n", (uint32_t) idata);
864 if (writeflag ==
MEM_WRITE && idata != ((64 - 1) << 20)) {
865 fatal(
"sh4_pcic: SH4_PCILSR0 unknown value" 866 " 0x%" PRIx32
"\n", (uint32_t) idata);
873 if (writeflag ==
MEM_WRITE && idata != 0xac000000) {
874 fatal(
"sh4_pcic: SH4_PCILAR0 unknown value" 875 " 0x%" PRIx32
"\n", (uint32_t) idata);
882 if (writeflag ==
MEM_WRITE && idata != ((64 - 1) << 20)) {
883 fatal(
"sh4_pcic: SH4_PCILSR1 unknown value" 884 " 0x%" PRIx32
"\n", (uint32_t) idata);
891 if (writeflag ==
MEM_WRITE && idata != 0xac000000) {
892 fatal(
"sh4_pcic: SH4_PCILAR1 unknown value" 893 " 0x%" PRIx32
"\n", (uint32_t) idata);
900 fatal(
"sh4_pcic: PCIMBR set to 0x%" PRIx32
", not" 901 " 0x%" PRIx32
"? TODO\n", (uint32_t) idata,
909 fatal(
"sh4_pcic: PCIIOBR set to 0x%" PRIx32
", not" 910 " 0x%" PRIx32
"? TODO\n", (uint32_t) idata,
919 int bus = (idata >> 16) & 0xff;
920 int dev = (idata >> 11) & 0x1f;
921 int func = (idata >> 8) & 7;
922 int reg = idata & 0xff;
930 &odata : &idata, len, writeflag);
933 default:
if (writeflag ==
MEM_READ) {
934 fatal(
"[ sh4_pcic: read from addr 0x%x: TODO ]\n",
937 fatal(
"[ sh4_pcic: write to addr 0x%x: 0x%x: TODO ]\n",
938 (
int)relative_addr, (
int)idata);
956 for (i=0; i<len; i++)
957 d->
sq[(relative_addr + i) %
sizeof(d->
sq)] =
data[i];
959 for (i=0; i<len; i++)
960 data[i] = d->
sq[(relative_addr + i) %
sizeof(d->
sq)];
970 uint64_t idata = 0, odata = 0;
971 int timer_nr = 0, dma_channel = 0;
979 if (relative_addr >= 0xff900000 && relative_addr <= 0xff97ffff) {
981 int v = (relative_addr >> 2) & 0xffff;
982 if (relative_addr & 0x00040000)
986 debug(
"[ sh4: sdmr%i set to 0x%04" PRIx16
" ]\n",
987 relative_addr & 0x00040000? 3 : 2, v);
992 switch (relative_addr) {
1008 unsigned int old_asid = cpu->
cd.
sh.
pteh 1071 idata &= ~SH4_MMUCR_TI;
1151 fatal(
"[ sh4 timer: TCOE not yet " 1163 if (idata & 1 && !(d->
tstr & 1))
1164 debug(
"[ sh4 timer: starting timer 0 ]\n");
1165 if (idata & 2 && !(d->
tstr & 2))
1166 debug(
"[ sh4 timer: starting timer 1 ]\n");
1167 if (idata & 4 && !(d->
tstr & 4))
1168 debug(
"[ sh4 timer: starting timer 2 ]\n");
1169 if (!(idata & 1) && d->
tstr & 1)
1170 debug(
"[ sh4 timer: stopping timer 0 ]\n");
1171 if (!(idata & 2) && d->
tstr & 2)
1172 debug(
"[ sh4 timer: stopping timer 1 ]\n");
1173 if (!(idata & 4) && d->
tstr & 4)
1174 debug(
"[ sh4 timer: stopping timer 2 ]\n");
1186 odata = d->
tcor[timer_nr];
1188 d->
tcor[timer_nr] = idata;
1198 odata = d->
tcnt[timer_nr];
1200 d->
tcnt[timer_nr] = idata;
1210 odata = d->
tcr[timer_nr];
1213 fatal(
"INTERNAL ERROR: pclock must be set" 1214 " for this machine. Aborting.\n");
1218 switch (idata & 3) {
1233 debug(
"[ sh4 timer %i clock set to %f Hz ]\n",
1238 fatal(
"Unimplemented SH4 timer control" 1239 " bits: 0x%08" PRIx32
". Aborting.\n",
1251 d->
tcr[timer_nr] = idata;
1300 if (idata & ~0x00ffffff) {
1301 fatal(
"[ SH4 DMA: Attempt to set top 8 " 1302 "bits of the count register? 0x%08" 1303 PRIx32
" ]\n", (uint32_t) idata);
1357 if (len !=
sizeof(uint16_t)) {
1358 fatal(
"Non-16-bit SH4_BCR2 access?\n");
1368 if (len !=
sizeof(uint16_t)) {
1369 fatal(
"Non-16-bit SH4_BCR3 access?\n");
1401 d->
bsc_mcr = idata & 0xf8bbffff;
1421 idata = (idata & ~RTCSR_CMF)
1470 if ((idata & 1) == 0 || (idata & 2) == 0)
1491 debug(
"[ sh4: pdtrb: write: TODO ]\n");
1494 debug(
"[ sh4: pdtrb: read: TODO ]\n");
1511 odata = sh4_sci_access(d, cpu,
1535 fatal(
"SH4 INTC: IRLM not yet " 1536 "supported. TODO\n");
1665 scif_reassert_interrupts(d);
1676 fatal(
"[ SCIF TX fifo overrun! ]\n");
1690 scif_reassert_interrupts(d);
1699 odata = x < 0? 0 : x;
1704 scif_reassert_interrupts(d);
1787 d->
rtc_reg[(relative_addr - 0xffc80000) / 4] = idata;
1790 odata = d->
rtc_reg[(relative_addr - 0xffc80000) / 4];
1800 fatal(
"SH4: TODO: RTC interrupt enable\n");
1812 if (idata != 0x02) {
1813 debug(
"[ SH4: TODO: RTC RCR2 value 0x%02x ignored. ]\n", (
int)idata);
1821 default:
if (writeflag ==
MEM_READ) {
1822 fatal(
"[ sh4: read from addr 0x%x ]\n",
1823 (
int)relative_addr);
1825 fatal(
"[ sh4: write to addr 0x%x: 0x%x ]\n",
1826 (
int)relative_addr, (
int)idata);
1843 char tmp[200], n[200];
1849 memset(d, 0,
sizeof(
struct sh4_data));
1864 0xe0000000, 0x04000000, dev_sh4_sq_access, d,
DM_DEFAULT, NULL);
1874 snprintf(tmp,
sizeof(tmp),
"%s.irq[0x%x]",
1877 snprintf(tmp,
sizeof(tmp),
"%s.irq[0x%x]",
1900 0x01000000, dev_sh4_itlb_aa_access, d,
DM_DEFAULT, NULL);
1904 0x01000000, dev_sh4_itlb_da1_access, d,
DM_DEFAULT, NULL);
1908 0x01000000, dev_sh4_utlb_aa_access, d,
DM_DEFAULT, NULL);
1912 0x01000000, dev_sh4_utlb_da1_access, d,
DM_DEFAULT, NULL);
1920 N_PCIC_REGS *
sizeof(uint32_t), dev_sh4_pcic_access, d,
1930 struct interrupt templ;
1931 snprintf(n,
sizeof(n),
"%s.pcic.%i",
1933 memset(&templ, 0,
sizeof(templ));
1941 snprintf(tmp,
sizeof(tmp),
"%s.irq[0x%x]",
1974 d->
tcor[0] = 0xffffffff; d->
tcnt[0] = 0xffffffff;
1975 d->
tcor[1] = 0xffffffff; d->
tcnt[1] = 0xffffffff;
1976 d->
tcor[2] = 0xffffffff; d->
tcnt[2] = 0xffffffff;
1978 snprintf(tmp,
sizeof(tmp),
"machine[0].cpu[0].irq[0x%x]",
1981 fatal(
"Could not find interrupt '%s'.\n", tmp);
1984 snprintf(tmp,
sizeof(tmp),
"machine[0].cpu[0].irq[0x%x]",
1987 fatal(
"Could not find interrupt '%s'.\n", tmp);
1990 snprintf(tmp,
sizeof(tmp),
"machine[0].cpu[0].irq[0x%x]",
1993 fatal(
"Could not find interrupt '%s'.\n", tmp);
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
#define BCR1_LITTLE_ENDIAN
void fatal(const char *fmt,...)
#define SH4_ITLB_AA_VPN_MASK
#define SH4_ITLB_AA_ASID_MASK
void(* interrupt_assert)(struct interrupt *)
#define SH_N_UTLB_ENTRIES
#define SH4_PTEH_VPN_MASK
DEVICE_ACCESS(sh4_itlb_aa)
#define SH4_INTEVT_SCIF_RXI
#define SH4_INTEVT_SCIF_TXI
uint32_t dmac_sar[N_SH4_DMA_CHANNELS]
void interrupt_handler_register(struct interrupt *templ)
void sh_update_interrupt_priorities(struct cpu *cpu)
void(* interrupt_deassert)(struct interrupt *)
#define PCI_PRODUCT_HITACHI_SH7751R
#define PCI_SUBCLASS_BRIDGE_HOST
struct interrupt cpu_pcic_interrupt[N_PCIC_IRQS]
void sh4_dmac_transfer(struct cpu *cpu, struct sh4_data *d, int channel)
#define PCI_ID_CODE(vid, pid)
#define SH4_UTLB_AA_ASID_MASK
void console_putchar(int handle, int ch)
int console_readchar(int handle)
void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr)
#define SH4_UTLB_AA_VPN_MASK
#define SH4_PTEH_ASID_MASK
int interrupt_handler_lookup(const char *name, struct interrupt *templ)
#define EMUL_LITTLE_ENDIAN
struct interrupt scif_tx_irq
#define CHECK_ALLOCATION(ptr)
#define EXPEVT_RESET_TLB_MULTI_HIT
#define SH_N_ITLB_ENTRIES
uint32_t itlb_lo[SH_N_ITLB_ENTRIES]
int console_charavail(int handle)
struct pci_data * pci_data
void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data, int bus, int device, int function, int reg)
int(* memory_rw)(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
#define SCIF_TX_FIFO_SIZE
#define SH_INTEVT_TMU0_TUNI0
uint32_t utlb_hi[SH_N_UTLB_ENTRIES]
struct interrupt scif_rx_irq
uint32_t dmac_chcr[N_SH4_DMA_CHANNELS]
struct timer * timer_add(double freq, void(*timer_tick)(struct timer *timer, void *extra), void *extra)
void dev_ram_init(struct machine *machine, uint64_t baseaddr, uint64_t length, int mode, uint64_t otheraddress, const char *name)
#define SH_INTEVT_TMU2_TUNI2
#define INTERRUPT_ASSERT(istruct)
uint8_t scif_tx_fifo[SCIF_TX_FIFO_SIZE+1]
struct interrupt timer_irq[4]
uint32_t tcnt[N_SH4_TIMERS]
int timer_interrupts_pending[N_SH4_TIMERS]
struct sh_cpu_type_def cpu_type
#define CHCR_SM_DECREMENTED
#define PCI_CLASS_CODE(mainclass, subclass, interface)
uint32_t pcic_reg[N_PCIC_REGS]
#define INTERRUPT_CONNECT(name, istruct)
uint32_t dmac_dar[N_SH4_DMA_CHANNELS]
#define SCIF_DELAYED_TX_VALUE
uint32_t dmac_tcr[N_SH4_DMA_CHANNELS]
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
int console_start_slave(struct machine *machine, const char *consolename, int use_for_input)
#define CHCR_DM_DECREMENTED
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
uint32_t itlb_hi[SH_N_ITLB_ENTRIES]
#define PCI_PRODUCT_HITACHI_SH7751
double timer_hz[N_SH4_TIMERS]
struct pci_data * bus_pci_init(struct machine *machine, const char *irq_path, uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset, uint64_t pci_portbase, uint64_t pci_membase, const char *pci_irqbase, uint64_t isa_portbase, uint64_t isa_membase, const char *isa_irqbase)
addr & if(addr >=0x24 &&page !=NULL)
void machine_add_tickfunction(struct machine *machine, void(*func)(struct cpu *, void *), void *extra, int clockshift)
uint32_t tcr[N_SH4_TIMERS]
#define CHCR_DM_INCREMENTED
#define CHCR_SM_INCREMENTED
void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data, uint64_t *data, int len, int writeflag)
#define SH4_PSEUDO_TIMER_HZ
uint32_t utlb_lo[SH_N_UTLB_ENTRIES]
#define PCI_VENDOR_HITACHI
size_t scif_tx_fifo_cursize
#define SH_INTEVT_TMU1_TUNI1
uint32_t tcor[N_SH4_TIMERS]
void(* invalidate_translation_caches)(struct cpu *, uint64_t paddr, int flags)
#define INTERRUPT_DEASSERT(istruct)