15 typedef int (ahc_reg_print_t)(u_int, u_int *, u_int);
16 typedef struct ahc_reg_parse_entry {
20 } ahc_reg_parse_entry_t;
23 #if AIC_DEBUG_REGISTERS 26 #define ahc_scsiseq_print(regvalue, cur_col, wrap) \ 27 ahc_print_register(NULL, 0, "SCSISEQ", 0x00, regvalue, cur_col, wrap) 30 #if AIC_DEBUG_REGISTERS 33 #define ahc_sxfrctl0_print(regvalue, cur_col, wrap) \ 34 ahc_print_register(NULL, 0, "SXFRCTL0", 0x01, regvalue, cur_col, wrap) 37 #if AIC_DEBUG_REGISTERS 40 #define ahc_sxfrctl1_print(regvalue, cur_col, wrap) \ 41 ahc_print_register(NULL, 0, "SXFRCTL1", 0x02, regvalue, cur_col, wrap) 44 #if AIC_DEBUG_REGISTERS 47 #define ahc_scsisigo_print(regvalue, cur_col, wrap) \ 48 ahc_print_register(NULL, 0, "SCSISIGO", 0x03, regvalue, cur_col, wrap) 51 #if AIC_DEBUG_REGISTERS 54 #define ahc_scsisigi_print(regvalue, cur_col, wrap) \ 55 ahc_print_register(NULL, 0, "SCSISIGI", 0x03, regvalue, cur_col, wrap) 58 #if AIC_DEBUG_REGISTERS 61 #define ahc_scsirate_print(regvalue, cur_col, wrap) \ 62 ahc_print_register(NULL, 0, "SCSIRATE", 0x04, regvalue, cur_col, wrap) 65 #if AIC_DEBUG_REGISTERS 68 #define ahc_scsiid_print(regvalue, cur_col, wrap) \ 69 ahc_print_register(NULL, 0, "SCSIID", 0x05, regvalue, cur_col, wrap) 72 #if AIC_DEBUG_REGISTERS 75 #define ahc_scsidatl_print(regvalue, cur_col, wrap) \ 76 ahc_print_register(NULL, 0, "SCSIDATL", 0x06, regvalue, cur_col, wrap) 79 #if AIC_DEBUG_REGISTERS 82 #define ahc_scsidath_print(regvalue, cur_col, wrap) \ 83 ahc_print_register(NULL, 0, "SCSIDATH", 0x07, regvalue, cur_col, wrap) 86 #if AIC_DEBUG_REGISTERS 89 #define ahc_stcnt_print(regvalue, cur_col, wrap) \ 90 ahc_print_register(NULL, 0, "STCNT", 0x08, regvalue, cur_col, wrap) 93 #if AIC_DEBUG_REGISTERS 96 #define ahc_optionmode_print(regvalue, cur_col, wrap) \ 97 ahc_print_register(NULL, 0, "OPTIONMODE", 0x08, regvalue, cur_col, wrap) 100 #if AIC_DEBUG_REGISTERS 103 #define ahc_targcrccnt_print(regvalue, cur_col, wrap) \ 104 ahc_print_register(NULL, 0, "TARGCRCCNT", 0x0a, regvalue, cur_col, wrap) 107 #if AIC_DEBUG_REGISTERS 110 #define ahc_clrsint0_print(regvalue, cur_col, wrap) \ 111 ahc_print_register(NULL, 0, "CLRSINT0", 0x0b, regvalue, cur_col, wrap) 114 #if AIC_DEBUG_REGISTERS 117 #define ahc_sstat0_print(regvalue, cur_col, wrap) \ 118 ahc_print_register(NULL, 0, "SSTAT0", 0x0b, regvalue, cur_col, wrap) 121 #if AIC_DEBUG_REGISTERS 124 #define ahc_clrsint1_print(regvalue, cur_col, wrap) \ 125 ahc_print_register(NULL, 0, "CLRSINT1", 0x0c, regvalue, cur_col, wrap) 128 #if AIC_DEBUG_REGISTERS 131 #define ahc_sstat1_print(regvalue, cur_col, wrap) \ 132 ahc_print_register(NULL, 0, "SSTAT1", 0x0c, regvalue, cur_col, wrap) 135 #if AIC_DEBUG_REGISTERS 138 #define ahc_sstat2_print(regvalue, cur_col, wrap) \ 139 ahc_print_register(NULL, 0, "SSTAT2", 0x0d, regvalue, cur_col, wrap) 142 #if AIC_DEBUG_REGISTERS 145 #define ahc_sstat3_print(regvalue, cur_col, wrap) \ 146 ahc_print_register(NULL, 0, "SSTAT3", 0x0e, regvalue, cur_col, wrap) 149 #if AIC_DEBUG_REGISTERS 152 #define ahc_scsiid_ultra2_print(regvalue, cur_col, wrap) \ 153 ahc_print_register(NULL, 0, "SCSIID_ULTRA2", 0x0f, regvalue, cur_col, wrap) 156 #if AIC_DEBUG_REGISTERS 159 #define ahc_simode0_print(regvalue, cur_col, wrap) \ 160 ahc_print_register(NULL, 0, "SIMODE0", 0x10, regvalue, cur_col, wrap) 163 #if AIC_DEBUG_REGISTERS 166 #define ahc_simode1_print(regvalue, cur_col, wrap) \ 167 ahc_print_register(NULL, 0, "SIMODE1", 0x11, regvalue, cur_col, wrap) 170 #if AIC_DEBUG_REGISTERS 173 #define ahc_scsibusl_print(regvalue, cur_col, wrap) \ 174 ahc_print_register(NULL, 0, "SCSIBUSL", 0x12, regvalue, cur_col, wrap) 177 #if AIC_DEBUG_REGISTERS 180 #define ahc_sxfrctl2_print(regvalue, cur_col, wrap) \ 181 ahc_print_register(NULL, 0, "SXFRCTL2", 0x13, regvalue, cur_col, wrap) 184 #if AIC_DEBUG_REGISTERS 187 #define ahc_scsibush_print(regvalue, cur_col, wrap) \ 188 ahc_print_register(NULL, 0, "SCSIBUSH", 0x13, regvalue, cur_col, wrap) 191 #if AIC_DEBUG_REGISTERS 194 #define ahc_shaddr_print(regvalue, cur_col, wrap) \ 195 ahc_print_register(NULL, 0, "SHADDR", 0x14, regvalue, cur_col, wrap) 198 #if AIC_DEBUG_REGISTERS 201 #define ahc_seltimer_print(regvalue, cur_col, wrap) \ 202 ahc_print_register(NULL, 0, "SELTIMER", 0x18, regvalue, cur_col, wrap) 205 #if AIC_DEBUG_REGISTERS 208 #define ahc_selid_print(regvalue, cur_col, wrap) \ 209 ahc_print_register(NULL, 0, "SELID", 0x19, regvalue, cur_col, wrap) 212 #if AIC_DEBUG_REGISTERS 215 #define ahc_scamctl_print(regvalue, cur_col, wrap) \ 216 ahc_print_register(NULL, 0, "SCAMCTL", 0x1a, regvalue, cur_col, wrap) 219 #if AIC_DEBUG_REGISTERS 222 #define ahc_targid_print(regvalue, cur_col, wrap) \ 223 ahc_print_register(NULL, 0, "TARGID", 0x1b, regvalue, cur_col, wrap) 226 #if AIC_DEBUG_REGISTERS 229 #define ahc_spiocap_print(regvalue, cur_col, wrap) \ 230 ahc_print_register(NULL, 0, "SPIOCAP", 0x1b, regvalue, cur_col, wrap) 233 #if AIC_DEBUG_REGISTERS 236 #define ahc_brdctl_print(regvalue, cur_col, wrap) \ 237 ahc_print_register(NULL, 0, "BRDCTL", 0x1d, regvalue, cur_col, wrap) 240 #if AIC_DEBUG_REGISTERS 243 #define ahc_seectl_print(regvalue, cur_col, wrap) \ 244 ahc_print_register(NULL, 0, "SEECTL", 0x1e, regvalue, cur_col, wrap) 247 #if AIC_DEBUG_REGISTERS 250 #define ahc_sblkctl_print(regvalue, cur_col, wrap) \ 251 ahc_print_register(NULL, 0, "SBLKCTL", 0x1f, regvalue, cur_col, wrap) 254 #if AIC_DEBUG_REGISTERS 257 #define ahc_busy_targets_print(regvalue, cur_col, wrap) \ 258 ahc_print_register(NULL, 0, "BUSY_TARGETS", 0x20, regvalue, cur_col, wrap) 261 #if AIC_DEBUG_REGISTERS 264 #define ahc_ultra_enb_print(regvalue, cur_col, wrap) \ 265 ahc_print_register(NULL, 0, "ULTRA_ENB", 0x30, regvalue, cur_col, wrap) 268 #if AIC_DEBUG_REGISTERS 271 #define ahc_disc_dsb_print(regvalue, cur_col, wrap) \ 272 ahc_print_register(NULL, 0, "DISC_DSB", 0x32, regvalue, cur_col, wrap) 275 #if AIC_DEBUG_REGISTERS 278 #define ahc_cmdsize_table_tail_print(regvalue, cur_col, wrap) \ 279 ahc_print_register(NULL, 0, "CMDSIZE_TABLE_TAIL", 0x34, regvalue, cur_col, wrap) 282 #if AIC_DEBUG_REGISTERS 285 #define ahc_mwi_residual_print(regvalue, cur_col, wrap) \ 286 ahc_print_register(NULL, 0, "MWI_RESIDUAL", 0x38, regvalue, cur_col, wrap) 289 #if AIC_DEBUG_REGISTERS 292 #define ahc_next_queued_scb_print(regvalue, cur_col, wrap) \ 293 ahc_print_register(NULL, 0, "NEXT_QUEUED_SCB", 0x39, regvalue, cur_col, wrap) 296 #if AIC_DEBUG_REGISTERS 299 #define ahc_msg_out_print(regvalue, cur_col, wrap) \ 300 ahc_print_register(NULL, 0, "MSG_OUT", 0x3a, regvalue, cur_col, wrap) 303 #if AIC_DEBUG_REGISTERS 306 #define ahc_dmaparams_print(regvalue, cur_col, wrap) \ 307 ahc_print_register(NULL, 0, "DMAPARAMS", 0x3b, regvalue, cur_col, wrap) 310 #if AIC_DEBUG_REGISTERS 313 #define ahc_seq_flags_print(regvalue, cur_col, wrap) \ 314 ahc_print_register(NULL, 0, "SEQ_FLAGS", 0x3c, regvalue, cur_col, wrap) 317 #if AIC_DEBUG_REGISTERS 320 #define ahc_saved_scsiid_print(regvalue, cur_col, wrap) \ 321 ahc_print_register(NULL, 0, "SAVED_SCSIID", 0x3d, regvalue, cur_col, wrap) 324 #if AIC_DEBUG_REGISTERS 327 #define ahc_saved_lun_print(regvalue, cur_col, wrap) \ 328 ahc_print_register(NULL, 0, "SAVED_LUN", 0x3e, regvalue, cur_col, wrap) 331 #if AIC_DEBUG_REGISTERS 334 #define ahc_lastphase_print(regvalue, cur_col, wrap) \ 335 ahc_print_register(NULL, 0, "LASTPHASE", 0x3f, regvalue, cur_col, wrap) 338 #if AIC_DEBUG_REGISTERS 341 #define ahc_waiting_scbh_print(regvalue, cur_col, wrap) \ 342 ahc_print_register(NULL, 0, "WAITING_SCBH", 0x40, regvalue, cur_col, wrap) 345 #if AIC_DEBUG_REGISTERS 348 #define ahc_disconnected_scbh_print(regvalue, cur_col, wrap) \ 349 ahc_print_register(NULL, 0, "DISCONNECTED_SCBH", 0x41, regvalue, cur_col, wrap) 352 #if AIC_DEBUG_REGISTERS 355 #define ahc_free_scbh_print(regvalue, cur_col, wrap) \ 356 ahc_print_register(NULL, 0, "FREE_SCBH", 0x42, regvalue, cur_col, wrap) 359 #if AIC_DEBUG_REGISTERS 362 #define ahc_complete_scbh_print(regvalue, cur_col, wrap) \ 363 ahc_print_register(NULL, 0, "COMPLETE_SCBH", 0x43, regvalue, cur_col, wrap) 366 #if AIC_DEBUG_REGISTERS 369 #define ahc_hscb_addr_print(regvalue, cur_col, wrap) \ 370 ahc_print_register(NULL, 0, "HSCB_ADDR", 0x44, regvalue, cur_col, wrap) 373 #if AIC_DEBUG_REGISTERS 376 #define ahc_shared_data_addr_print(regvalue, cur_col, wrap) \ 377 ahc_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x48, regvalue, cur_col, wrap) 380 #if AIC_DEBUG_REGISTERS 383 #define ahc_kernel_qinpos_print(regvalue, cur_col, wrap) \ 384 ahc_print_register(NULL, 0, "KERNEL_QINPOS", 0x4c, regvalue, cur_col, wrap) 387 #if AIC_DEBUG_REGISTERS 390 #define ahc_qinpos_print(regvalue, cur_col, wrap) \ 391 ahc_print_register(NULL, 0, "QINPOS", 0x4d, regvalue, cur_col, wrap) 394 #if AIC_DEBUG_REGISTERS 397 #define ahc_qoutpos_print(regvalue, cur_col, wrap) \ 398 ahc_print_register(NULL, 0, "QOUTPOS", 0x4e, regvalue, cur_col, wrap) 401 #if AIC_DEBUG_REGISTERS 404 #define ahc_kernel_tqinpos_print(regvalue, cur_col, wrap) \ 405 ahc_print_register(NULL, 0, "KERNEL_TQINPOS", 0x4f, regvalue, cur_col, wrap) 408 #if AIC_DEBUG_REGISTERS 411 #define ahc_tqinpos_print(regvalue, cur_col, wrap) \ 412 ahc_print_register(NULL, 0, "TQINPOS", 0x50, regvalue, cur_col, wrap) 415 #if AIC_DEBUG_REGISTERS 418 #define ahc_arg_1_print(regvalue, cur_col, wrap) \ 419 ahc_print_register(NULL, 0, "ARG_1", 0x51, regvalue, cur_col, wrap) 422 #if AIC_DEBUG_REGISTERS 425 #define ahc_arg_2_print(regvalue, cur_col, wrap) \ 426 ahc_print_register(NULL, 0, "ARG_2", 0x52, regvalue, cur_col, wrap) 429 #if AIC_DEBUG_REGISTERS 432 #define ahc_last_msg_print(regvalue, cur_col, wrap) \ 433 ahc_print_register(NULL, 0, "LAST_MSG", 0x53, regvalue, cur_col, wrap) 436 #if AIC_DEBUG_REGISTERS 439 #define ahc_scsiseq_template_print(regvalue, cur_col, wrap) \ 440 ahc_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x54, regvalue, cur_col, wrap) 443 #if AIC_DEBUG_REGISTERS 446 #define ahc_data_count_odd_print(regvalue, cur_col, wrap) \ 447 ahc_print_register(NULL, 0, "DATA_COUNT_ODD", 0x55, regvalue, cur_col, wrap) 450 #if AIC_DEBUG_REGISTERS 453 #define ahc_ha_274_biosglobal_print(regvalue, cur_col, wrap) \ 454 ahc_print_register(NULL, 0, "HA_274_BIOSGLOBAL", 0x56, regvalue, cur_col, wrap) 457 #if AIC_DEBUG_REGISTERS 460 #define ahc_seq_flags2_print(regvalue, cur_col, wrap) \ 461 ahc_print_register(NULL, 0, "SEQ_FLAGS2", 0x57, regvalue, cur_col, wrap) 464 #if AIC_DEBUG_REGISTERS 467 #define ahc_scsiconf_print(regvalue, cur_col, wrap) \ 468 ahc_print_register(NULL, 0, "SCSICONF", 0x5a, regvalue, cur_col, wrap) 471 #if AIC_DEBUG_REGISTERS 474 #define ahc_intdef_print(regvalue, cur_col, wrap) \ 475 ahc_print_register(NULL, 0, "INTDEF", 0x5c, regvalue, cur_col, wrap) 478 #if AIC_DEBUG_REGISTERS 481 #define ahc_hostconf_print(regvalue, cur_col, wrap) \ 482 ahc_print_register(NULL, 0, "HOSTCONF", 0x5d, regvalue, cur_col, wrap) 485 #if AIC_DEBUG_REGISTERS 488 #define ahc_ha_274_biosctrl_print(regvalue, cur_col, wrap) \ 489 ahc_print_register(NULL, 0, "HA_274_BIOSCTRL", 0x5f, regvalue, cur_col, wrap) 492 #if AIC_DEBUG_REGISTERS 495 #define ahc_seqctl_print(regvalue, cur_col, wrap) \ 496 ahc_print_register(NULL, 0, "SEQCTL", 0x60, regvalue, cur_col, wrap) 499 #if AIC_DEBUG_REGISTERS 502 #define ahc_seqram_print(regvalue, cur_col, wrap) \ 503 ahc_print_register(NULL, 0, "SEQRAM", 0x61, regvalue, cur_col, wrap) 506 #if AIC_DEBUG_REGISTERS 509 #define ahc_seqaddr0_print(regvalue, cur_col, wrap) \ 510 ahc_print_register(NULL, 0, "SEQADDR0", 0x62, regvalue, cur_col, wrap) 513 #if AIC_DEBUG_REGISTERS 516 #define ahc_seqaddr1_print(regvalue, cur_col, wrap) \ 517 ahc_print_register(NULL, 0, "SEQADDR1", 0x63, regvalue, cur_col, wrap) 520 #if AIC_DEBUG_REGISTERS 523 #define ahc_accum_print(regvalue, cur_col, wrap) \ 524 ahc_print_register(NULL, 0, "ACCUM", 0x64, regvalue, cur_col, wrap) 527 #if AIC_DEBUG_REGISTERS 530 #define ahc_sindex_print(regvalue, cur_col, wrap) \ 531 ahc_print_register(NULL, 0, "SINDEX", 0x65, regvalue, cur_col, wrap) 534 #if AIC_DEBUG_REGISTERS 537 #define ahc_dindex_print(regvalue, cur_col, wrap) \ 538 ahc_print_register(NULL, 0, "DINDEX", 0x66, regvalue, cur_col, wrap) 541 #if AIC_DEBUG_REGISTERS 544 #define ahc_allones_print(regvalue, cur_col, wrap) \ 545 ahc_print_register(NULL, 0, "ALLONES", 0x69, regvalue, cur_col, wrap) 548 #if AIC_DEBUG_REGISTERS 551 #define ahc_none_print(regvalue, cur_col, wrap) \ 552 ahc_print_register(NULL, 0, "NONE", 0x6a, regvalue, cur_col, wrap) 555 #if AIC_DEBUG_REGISTERS 558 #define ahc_allzeros_print(regvalue, cur_col, wrap) \ 559 ahc_print_register(NULL, 0, "ALLZEROS", 0x6a, regvalue, cur_col, wrap) 562 #if AIC_DEBUG_REGISTERS 565 #define ahc_flags_print(regvalue, cur_col, wrap) \ 566 ahc_print_register(NULL, 0, "FLAGS", 0x6b, regvalue, cur_col, wrap) 569 #if AIC_DEBUG_REGISTERS 572 #define ahc_sindir_print(regvalue, cur_col, wrap) \ 573 ahc_print_register(NULL, 0, "SINDIR", 0x6c, regvalue, cur_col, wrap) 576 #if AIC_DEBUG_REGISTERS 579 #define ahc_dindir_print(regvalue, cur_col, wrap) \ 580 ahc_print_register(NULL, 0, "DINDIR", 0x6d, regvalue, cur_col, wrap) 583 #if AIC_DEBUG_REGISTERS 586 #define ahc_function1_print(regvalue, cur_col, wrap) \ 587 ahc_print_register(NULL, 0, "FUNCTION1", 0x6e, regvalue, cur_col, wrap) 590 #if AIC_DEBUG_REGISTERS 593 #define ahc_stack_print(regvalue, cur_col, wrap) \ 594 ahc_print_register(NULL, 0, "STACK", 0x6f, regvalue, cur_col, wrap) 597 #if AIC_DEBUG_REGISTERS 600 #define ahc_targ_offset_print(regvalue, cur_col, wrap) \ 601 ahc_print_register(NULL, 0, "TARG_OFFSET", 0x70, regvalue, cur_col, wrap) 604 #if AIC_DEBUG_REGISTERS 607 #define ahc_sram_base_print(regvalue, cur_col, wrap) \ 608 ahc_print_register(NULL, 0, "SRAM_BASE", 0x70, regvalue, cur_col, wrap) 611 #if AIC_DEBUG_REGISTERS 614 #define ahc_bctl_print(regvalue, cur_col, wrap) \ 615 ahc_print_register(NULL, 0, "BCTL", 0x84, regvalue, cur_col, wrap) 618 #if AIC_DEBUG_REGISTERS 621 #define ahc_dscommand0_print(regvalue, cur_col, wrap) \ 622 ahc_print_register(NULL, 0, "DSCOMMAND0", 0x84, regvalue, cur_col, wrap) 625 #if AIC_DEBUG_REGISTERS 628 #define ahc_bustime_print(regvalue, cur_col, wrap) \ 629 ahc_print_register(NULL, 0, "BUSTIME", 0x85, regvalue, cur_col, wrap) 632 #if AIC_DEBUG_REGISTERS 635 #define ahc_dscommand1_print(regvalue, cur_col, wrap) \ 636 ahc_print_register(NULL, 0, "DSCOMMAND1", 0x85, regvalue, cur_col, wrap) 639 #if AIC_DEBUG_REGISTERS 642 #define ahc_busspd_print(regvalue, cur_col, wrap) \ 643 ahc_print_register(NULL, 0, "BUSSPD", 0x86, regvalue, cur_col, wrap) 646 #if AIC_DEBUG_REGISTERS 649 #define ahc_dspcistatus_print(regvalue, cur_col, wrap) \ 650 ahc_print_register(NULL, 0, "DSPCISTATUS", 0x86, regvalue, cur_col, wrap) 653 #if AIC_DEBUG_REGISTERS 656 #define ahc_hs_mailbox_print(regvalue, cur_col, wrap) \ 657 ahc_print_register(NULL, 0, "HS_MAILBOX", 0x86, regvalue, cur_col, wrap) 660 #if AIC_DEBUG_REGISTERS 663 #define ahc_hcntrl_print(regvalue, cur_col, wrap) \ 664 ahc_print_register(NULL, 0, "HCNTRL", 0x87, regvalue, cur_col, wrap) 667 #if AIC_DEBUG_REGISTERS 670 #define ahc_haddr_print(regvalue, cur_col, wrap) \ 671 ahc_print_register(NULL, 0, "HADDR", 0x88, regvalue, cur_col, wrap) 674 #if AIC_DEBUG_REGISTERS 677 #define ahc_hcnt_print(regvalue, cur_col, wrap) \ 678 ahc_print_register(NULL, 0, "HCNT", 0x8c, regvalue, cur_col, wrap) 681 #if AIC_DEBUG_REGISTERS 684 #define ahc_scbptr_print(regvalue, cur_col, wrap) \ 685 ahc_print_register(NULL, 0, "SCBPTR", 0x90, regvalue, cur_col, wrap) 688 #if AIC_DEBUG_REGISTERS 691 #define ahc_intstat_print(regvalue, cur_col, wrap) \ 692 ahc_print_register(NULL, 0, "INTSTAT", 0x91, regvalue, cur_col, wrap) 695 #if AIC_DEBUG_REGISTERS 698 #define ahc_error_print(regvalue, cur_col, wrap) \ 699 ahc_print_register(NULL, 0, "ERROR", 0x92, regvalue, cur_col, wrap) 702 #if AIC_DEBUG_REGISTERS 705 #define ahc_clrint_print(regvalue, cur_col, wrap) \ 706 ahc_print_register(NULL, 0, "CLRINT", 0x92, regvalue, cur_col, wrap) 709 #if AIC_DEBUG_REGISTERS 712 #define ahc_dfcntrl_print(regvalue, cur_col, wrap) \ 713 ahc_print_register(NULL, 0, "DFCNTRL", 0x93, regvalue, cur_col, wrap) 716 #if AIC_DEBUG_REGISTERS 719 #define ahc_dfstatus_print(regvalue, cur_col, wrap) \ 720 ahc_print_register(NULL, 0, "DFSTATUS", 0x94, regvalue, cur_col, wrap) 723 #if AIC_DEBUG_REGISTERS 726 #define ahc_dfwaddr_print(regvalue, cur_col, wrap) \ 727 ahc_print_register(NULL, 0, "DFWADDR", 0x95, regvalue, cur_col, wrap) 730 #if AIC_DEBUG_REGISTERS 733 #define ahc_dfraddr_print(regvalue, cur_col, wrap) \ 734 ahc_print_register(NULL, 0, "DFRADDR", 0x97, regvalue, cur_col, wrap) 737 #if AIC_DEBUG_REGISTERS 740 #define ahc_dfdat_print(regvalue, cur_col, wrap) \ 741 ahc_print_register(NULL, 0, "DFDAT", 0x99, regvalue, cur_col, wrap) 744 #if AIC_DEBUG_REGISTERS 747 #define ahc_scbcnt_print(regvalue, cur_col, wrap) \ 748 ahc_print_register(NULL, 0, "SCBCNT", 0x9a, regvalue, cur_col, wrap) 751 #if AIC_DEBUG_REGISTERS 754 #define ahc_qinfifo_print(regvalue, cur_col, wrap) \ 755 ahc_print_register(NULL, 0, "QINFIFO", 0x9b, regvalue, cur_col, wrap) 758 #if AIC_DEBUG_REGISTERS 761 #define ahc_qincnt_print(regvalue, cur_col, wrap) \ 762 ahc_print_register(NULL, 0, "QINCNT", 0x9c, regvalue, cur_col, wrap) 765 #if AIC_DEBUG_REGISTERS 768 #define ahc_crccontrol1_print(regvalue, cur_col, wrap) \ 769 ahc_print_register(NULL, 0, "CRCCONTROL1", 0x9d, regvalue, cur_col, wrap) 772 #if AIC_DEBUG_REGISTERS 775 #define ahc_qoutfifo_print(regvalue, cur_col, wrap) \ 776 ahc_print_register(NULL, 0, "QOUTFIFO", 0x9d, regvalue, cur_col, wrap) 779 #if AIC_DEBUG_REGISTERS 782 #define ahc_scsiphase_print(regvalue, cur_col, wrap) \ 783 ahc_print_register(NULL, 0, "SCSIPHASE", 0x9e, regvalue, cur_col, wrap) 786 #if AIC_DEBUG_REGISTERS 789 #define ahc_qoutcnt_print(regvalue, cur_col, wrap) \ 790 ahc_print_register(NULL, 0, "QOUTCNT", 0x9e, regvalue, cur_col, wrap) 793 #if AIC_DEBUG_REGISTERS 796 #define ahc_sfunct_print(regvalue, cur_col, wrap) \ 797 ahc_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap) 800 #if AIC_DEBUG_REGISTERS 803 #define ahc_scb_base_print(regvalue, cur_col, wrap) \ 804 ahc_print_register(NULL, 0, "SCB_BASE", 0xa0, regvalue, cur_col, wrap) 807 #if AIC_DEBUG_REGISTERS 810 #define ahc_scb_cdb_ptr_print(regvalue, cur_col, wrap) \ 811 ahc_print_register(NULL, 0, "SCB_CDB_PTR", 0xa0, regvalue, cur_col, wrap) 814 #if AIC_DEBUG_REGISTERS 817 #define ahc_scb_residual_sgptr_print(regvalue, cur_col, wrap) \ 818 ahc_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0xa4, regvalue, cur_col, wrap) 821 #if AIC_DEBUG_REGISTERS 824 #define ahc_scb_scsi_status_print(regvalue, cur_col, wrap) \ 825 ahc_print_register(NULL, 0, "SCB_SCSI_STATUS", 0xa8, regvalue, cur_col, wrap) 828 #if AIC_DEBUG_REGISTERS 831 #define ahc_scb_target_phases_print(regvalue, cur_col, wrap) \ 832 ahc_print_register(NULL, 0, "SCB_TARGET_PHASES", 0xa9, regvalue, cur_col, wrap) 835 #if AIC_DEBUG_REGISTERS 838 #define ahc_scb_target_data_dir_print(regvalue, cur_col, wrap) \ 839 ahc_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0xaa, regvalue, cur_col, wrap) 842 #if AIC_DEBUG_REGISTERS 845 #define ahc_scb_target_itag_print(regvalue, cur_col, wrap) \ 846 ahc_print_register(NULL, 0, "SCB_TARGET_ITAG", 0xab, regvalue, cur_col, wrap) 849 #if AIC_DEBUG_REGISTERS 852 #define ahc_scb_dataptr_print(regvalue, cur_col, wrap) \ 853 ahc_print_register(NULL, 0, "SCB_DATAPTR", 0xac, regvalue, cur_col, wrap) 856 #if AIC_DEBUG_REGISTERS 859 #define ahc_scb_datacnt_print(regvalue, cur_col, wrap) \ 860 ahc_print_register(NULL, 0, "SCB_DATACNT", 0xb0, regvalue, cur_col, wrap) 863 #if AIC_DEBUG_REGISTERS 866 #define ahc_scb_sgptr_print(regvalue, cur_col, wrap) \ 867 ahc_print_register(NULL, 0, "SCB_SGPTR", 0xb4, regvalue, cur_col, wrap) 870 #if AIC_DEBUG_REGISTERS 873 #define ahc_scb_control_print(regvalue, cur_col, wrap) \ 874 ahc_print_register(NULL, 0, "SCB_CONTROL", 0xb8, regvalue, cur_col, wrap) 877 #if AIC_DEBUG_REGISTERS 880 #define ahc_scb_scsiid_print(regvalue, cur_col, wrap) \ 881 ahc_print_register(NULL, 0, "SCB_SCSIID", 0xb9, regvalue, cur_col, wrap) 884 #if AIC_DEBUG_REGISTERS 887 #define ahc_scb_lun_print(regvalue, cur_col, wrap) \ 888 ahc_print_register(NULL, 0, "SCB_LUN", 0xba, regvalue, cur_col, wrap) 891 #if AIC_DEBUG_REGISTERS 894 #define ahc_scb_tag_print(regvalue, cur_col, wrap) \ 895 ahc_print_register(NULL, 0, "SCB_TAG", 0xbb, regvalue, cur_col, wrap) 898 #if AIC_DEBUG_REGISTERS 901 #define ahc_scb_cdb_len_print(regvalue, cur_col, wrap) \ 902 ahc_print_register(NULL, 0, "SCB_CDB_LEN", 0xbc, regvalue, cur_col, wrap) 905 #if AIC_DEBUG_REGISTERS 908 #define ahc_scb_scsirate_print(regvalue, cur_col, wrap) \ 909 ahc_print_register(NULL, 0, "SCB_SCSIRATE", 0xbd, regvalue, cur_col, wrap) 912 #if AIC_DEBUG_REGISTERS 915 #define ahc_scb_scsioffset_print(regvalue, cur_col, wrap) \ 916 ahc_print_register(NULL, 0, "SCB_SCSIOFFSET", 0xbe, regvalue, cur_col, wrap) 919 #if AIC_DEBUG_REGISTERS 922 #define ahc_scb_next_print(regvalue, cur_col, wrap) \ 923 ahc_print_register(NULL, 0, "SCB_NEXT", 0xbf, regvalue, cur_col, wrap) 926 #if AIC_DEBUG_REGISTERS 929 #define ahc_scb_64_spare_print(regvalue, cur_col, wrap) \ 930 ahc_print_register(NULL, 0, "SCB_64_SPARE", 0xc0, regvalue, cur_col, wrap) 933 #if AIC_DEBUG_REGISTERS 936 #define ahc_seectl_2840_print(regvalue, cur_col, wrap) \ 937 ahc_print_register(NULL, 0, "SEECTL_2840", 0xc0, regvalue, cur_col, wrap) 940 #if AIC_DEBUG_REGISTERS 943 #define ahc_status_2840_print(regvalue, cur_col, wrap) \ 944 ahc_print_register(NULL, 0, "STATUS_2840", 0xc1, regvalue, cur_col, wrap) 947 #if AIC_DEBUG_REGISTERS 950 #define ahc_scb_64_btt_print(regvalue, cur_col, wrap) \ 951 ahc_print_register(NULL, 0, "SCB_64_BTT", 0xd0, regvalue, cur_col, wrap) 954 #if AIC_DEBUG_REGISTERS 957 #define ahc_cchaddr_print(regvalue, cur_col, wrap) \ 958 ahc_print_register(NULL, 0, "CCHADDR", 0xe0, regvalue, cur_col, wrap) 961 #if AIC_DEBUG_REGISTERS 964 #define ahc_cchcnt_print(regvalue, cur_col, wrap) \ 965 ahc_print_register(NULL, 0, "CCHCNT", 0xe8, regvalue, cur_col, wrap) 968 #if AIC_DEBUG_REGISTERS 971 #define ahc_ccsgram_print(regvalue, cur_col, wrap) \ 972 ahc_print_register(NULL, 0, "CCSGRAM", 0xe9, regvalue, cur_col, wrap) 975 #if AIC_DEBUG_REGISTERS 978 #define ahc_ccsgaddr_print(regvalue, cur_col, wrap) \ 979 ahc_print_register(NULL, 0, "CCSGADDR", 0xea, regvalue, cur_col, wrap) 982 #if AIC_DEBUG_REGISTERS 985 #define ahc_ccsgctl_print(regvalue, cur_col, wrap) \ 986 ahc_print_register(NULL, 0, "CCSGCTL", 0xeb, regvalue, cur_col, wrap) 989 #if AIC_DEBUG_REGISTERS 992 #define ahc_ccscbram_print(regvalue, cur_col, wrap) \ 993 ahc_print_register(NULL, 0, "CCSCBRAM", 0xec, regvalue, cur_col, wrap) 996 #if AIC_DEBUG_REGISTERS 999 #define ahc_ccscbaddr_print(regvalue, cur_col, wrap) \ 1000 ahc_print_register(NULL, 0, "CCSCBADDR", 0xed, regvalue, cur_col, wrap) 1003 #if AIC_DEBUG_REGISTERS 1006 #define ahc_ccscbctl_print(regvalue, cur_col, wrap) \ 1007 ahc_print_register(NULL, 0, "CCSCBCTL", 0xee, regvalue, cur_col, wrap) 1010 #if AIC_DEBUG_REGISTERS 1013 #define ahc_ccscbcnt_print(regvalue, cur_col, wrap) \ 1014 ahc_print_register(NULL, 0, "CCSCBCNT", 0xef, regvalue, cur_col, wrap) 1017 #if AIC_DEBUG_REGISTERS 1020 #define ahc_scbbaddr_print(regvalue, cur_col, wrap) \ 1021 ahc_print_register(NULL, 0, "SCBBADDR", 0xf0, regvalue, cur_col, wrap) 1024 #if AIC_DEBUG_REGISTERS 1027 #define ahc_ccscbptr_print(regvalue, cur_col, wrap) \ 1028 ahc_print_register(NULL, 0, "CCSCBPTR", 0xf1, regvalue, cur_col, wrap) 1031 #if AIC_DEBUG_REGISTERS 1034 #define ahc_hnscb_qoff_print(regvalue, cur_col, wrap) \ 1035 ahc_print_register(NULL, 0, "HNSCB_QOFF", 0xf4, regvalue, cur_col, wrap) 1038 #if AIC_DEBUG_REGISTERS 1041 #define ahc_snscb_qoff_print(regvalue, cur_col, wrap) \ 1042 ahc_print_register(NULL, 0, "SNSCB_QOFF", 0xf6, regvalue, cur_col, wrap) 1045 #if AIC_DEBUG_REGISTERS 1048 #define ahc_sdscb_qoff_print(regvalue, cur_col, wrap) \ 1049 ahc_print_register(NULL, 0, "SDSCB_QOFF", 0xf8, regvalue, cur_col, wrap) 1052 #if AIC_DEBUG_REGISTERS 1055 #define ahc_qoff_ctlsta_print(regvalue, cur_col, wrap) \ 1056 ahc_print_register(NULL, 0, "QOFF_CTLSTA", 0xfa, regvalue, cur_col, wrap) 1059 #if AIC_DEBUG_REGISTERS 1062 #define ahc_dff_thrsh_print(regvalue, cur_col, wrap) \ 1063 ahc_print_register(NULL, 0, "DFF_THRSH", 0xfb, regvalue, cur_col, wrap) 1066 #if AIC_DEBUG_REGISTERS 1069 #define ahc_sg_cache_shadow_print(regvalue, cur_col, wrap) \ 1070 ahc_print_register(NULL, 0, "SG_CACHE_SHADOW", 0xfc, regvalue, cur_col, wrap) 1073 #if AIC_DEBUG_REGISTERS 1076 #define ahc_sg_cache_pre_print(regvalue, cur_col, wrap) \ 1077 ahc_print_register(NULL, 0, "SG_CACHE_PRE", 0xfc, regvalue, cur_col, wrap) 1081 #define SCSISEQ 0x00 1083 #define SCSIRSTO 0x01 1085 #define SXFRCTL0 0x01 1089 #define CLRSTCNT 0x10 1094 #define SXFRCTL1 0x02 1095 #define STIMESEL 0x18 1096 #define BITBUCKET 0x80 1097 #define SWRAPEN 0x40 1098 #define ENSTIMER 0x04 1099 #define ACTNEGEN 0x02 1102 #define SCSISIGO 0x03 1112 #define SCSISIGI 0x03 1113 #define P_DATAIN_DT 0x60 1114 #define P_DATAOUT_DT 0x20 1121 #define SCSIRATE 0x04 1123 #define SXFR_ULTRA2 0x0f 1125 #define WIDEXFER 0x80 1126 #define ENABLE_CRC 0x40 1127 #define SINGLE_EDGE 0x10 1130 #define SCSIOFFSET 0x05 1131 #define SOFS_ULTRA2 0x7f 1133 #define SCSIDATL 0x06 1135 #define SCSIDATH 0x07 1139 #define OPTIONMODE 0x08 1140 #define OPTIONMODE_DEFAULTS 0x03 1141 #define AUTORATEEN 0x80 1142 #define AUTOACKEN 0x40 1143 #define ATNMGMNTEN 0x20 1144 #define BUSFREEREV 0x10 1145 #define EXPPHASEDIS 0x08 1146 #define SCSIDATL_IMGEN 0x04 1147 #define AUTO_MSGOUT_DE 0x02 1148 #define DIS_MSGIN_DUALEDGE 0x01 1150 #define TARGCRCCNT 0x0a 1152 #define CLRSINT0 0x0b 1153 #define CLRSELDO 0x40 1154 #define CLRSELDI 0x20 1155 #define CLRSELINGO 0x10 1156 #define CLRSWRAP 0x08 1157 #define CLRIOERR 0x08 1158 #define CLRSPIORDY 0x02 1164 #define SELINGO 0x10 1168 #define SPIORDY 0x02 1169 #define DMADONE 0x01 1171 #define CLRSINT1 0x0c 1172 #define CLRSELTIMEO 0x80 1173 #define CLRATNO 0x40 1174 #define CLRSCSIRSTI 0x20 1175 #define CLRBUSFREE 0x08 1176 #define CLRSCSIPERR 0x04 1177 #define CLRPHASECHG 0x02 1178 #define CLRREQINIT 0x01 1182 #define ATNTARG 0x40 1183 #define SCSIRSTI 0x20 1184 #define PHASEMIS 0x10 1185 #define BUSFREE 0x08 1186 #define SCSIPERR 0x04 1187 #define PHASECHG 0x02 1188 #define REQINIT 0x01 1192 #define OVERRUN 0x80 1193 #define SHVALID 0x40 1194 #define EXP_ACTIVE 0x10 1195 #define CRCVALERR 0x08 1196 #define CRCENDERR 0x04 1197 #define CRCREQERR 0x02 1198 #define DUAL_EDGE_ERR 0x01 1201 #define SCSICNT 0xf0 1202 #define U2OFFCNT 0x7f 1205 #define SCSIID_ULTRA2 0x0f 1207 #define SIMODE0 0x10 1208 #define ENSELDO 0x40 1209 #define ENSELDI 0x20 1210 #define ENSELINGO 0x10 1211 #define ENIOERR 0x08 1212 #define ENSWRAP 0x08 1213 #define ENSDONE 0x04 1214 #define ENSPIORDY 0x02 1215 #define ENDMADONE 0x01 1217 #define SIMODE1 0x11 1218 #define ENSELTIMO 0x80 1219 #define ENATNTARG 0x40 1220 #define ENSCSIRST 0x20 1221 #define ENPHASEMIS 0x10 1222 #define ENBUSFREE 0x08 1223 #define ENSCSIPERR 0x04 1224 #define ENPHASECHG 0x02 1225 #define ENREQINIT 0x01 1227 #define SCSIBUSL 0x12 1229 #define SXFRCTL2 0x13 1230 #define ASYNC_SETUP 0x07 1231 #define AUTORSTDIS 0x10 1232 #define CMDDMAEN 0x08 1234 #define SCSIBUSH 0x13 1238 #define SELTIMER 0x18 1239 #define TARGIDIN 0x18 1248 #define SELID_MASK 0xf0 1251 #define SCAMCTL 0x1a 1252 #define SCAMLVL 0x03 1253 #define ENSCAMSELO 0x80 1254 #define CLRSCAMSELID 0x40 1255 #define ALTSTIM 0x20 1256 #define DFLTTID 0x10 1260 #define SPIOCAP 0x1b 1263 #define SOFTCMDEN 0x20 1264 #define EXT_BRDCTL 0x10 1265 #define SEEPROM 0x08 1268 #define SSPIOCPS 0x01 1271 #define BRDDAT7 0x80 1272 #define BRDDAT6 0x40 1273 #define BRDDAT5 0x20 1274 #define BRDDAT4 0x10 1277 #define BRDDAT3 0x08 1278 #define BRDDAT2 0x04 1280 #define BRDCTL1 0x02 1281 #define BRDRW_ULTRA2 0x02 1282 #define BRDCTL0 0x01 1283 #define BRDSTB_ULTRA2 0x01 1286 #define EXTARBACK 0x80 1287 #define EXTARBREQ 0x40 1295 #define SBLKCTL 0x1f 1296 #define DIAGLEDEN 0x80 1297 #define DIAGLEDON 0x40 1298 #define AUTOFLUSHDIS 0x20 1300 #define SELBUSB 0x08 1302 #define SELWIDE 0x02 1305 #define BUSY_TARGETS 0x20 1306 #define TARG_SCSIRATE 0x20 1308 #define ULTRA_ENB 0x30 1309 #define CMDSIZE_TABLE 0x30 1311 #define DISC_DSB 0x32 1313 #define CMDSIZE_TABLE_TAIL 0x34 1315 #define MWI_RESIDUAL 0x38 1316 #define TARG_IMMEDIATE_SCB 0x38 1318 #define NEXT_QUEUED_SCB 0x39 1320 #define MSG_OUT 0x3a 1322 #define DMAPARAMS 0x3b 1323 #define PRELOADEN 0x80 1324 #define WIDEODD 0x40 1326 #define SDMAENACK 0x10 1329 #define HDMAENACK 0x08 1330 #define DIRECTION 0x04 1331 #define FIFOFLUSH 0x02 1332 #define FIFORESET 0x01 1334 #define SEQ_FLAGS 0x3c 1335 #define NOT_IDENTIFIED 0x80 1336 #define NO_CDB_SENT 0x40 1337 #define TARGET_CMD_IS_TAGGED 0x40 1339 #define TARG_CMD_PENDING 0x10 1340 #define CMDPHASE_PENDING 0x08 1341 #define DPHASE_PENDING 0x04 1342 #define SPHASE_PENDING 0x02 1343 #define NO_DISCONNECT 0x01 1345 #define SAVED_SCSIID 0x3d 1347 #define SAVED_LUN 0x3e 1349 #define LASTPHASE 0x3f 1350 #define PHASE_MASK 0xe0 1351 #define P_MESGIN 0xe0 1352 #define P_STATUS 0xc0 1353 #define P_MESGOUT 0xa0 1354 #define P_COMMAND 0x80 1355 #define P_DATAIN 0x40 1356 #define P_BUSFREE 0x01 1357 #define P_DATAOUT 0x00 1362 #define WAITING_SCBH 0x40 1364 #define DISCONNECTED_SCBH 0x41 1366 #define FREE_SCBH 0x42 1368 #define COMPLETE_SCBH 0x43 1370 #define HSCB_ADDR 0x44 1372 #define SHARED_DATA_ADDR 0x48 1374 #define KERNEL_QINPOS 0x4c 1378 #define QOUTPOS 0x4e 1380 #define KERNEL_TQINPOS 0x4f 1382 #define TQINPOS 0x50 1385 #define RETURN_1 0x51 1386 #define SEND_MSG 0x80 1387 #define SEND_SENSE 0x40 1388 #define SEND_REJ 0x20 1389 #define MSGOUT_PHASEMIS 0x10 1390 #define EXIT_MSG_LOOP 0x08 1391 #define CONT_MSG_LOOP 0x04 1392 #define CONT_TARG_SESSION 0x02 1395 #define RETURN_2 0x52 1397 #define LAST_MSG 0x53 1399 #define SCSISEQ_TEMPLATE 0x54 1402 #define ENRSELI 0x10 1403 #define ENAUTOATNO 0x08 1404 #define ENAUTOATNI 0x04 1405 #define ENAUTOATNP 0x02 1407 #define DATA_COUNT_ODD 0x55 1409 #define HA_274_BIOSGLOBAL 0x56 1410 #define INITIATOR_TAG 0x56 1411 #define HA_274_EXTENDED_TRANS 0x01 1413 #define SEQ_FLAGS2 0x57 1414 #define TARGET_MSG_PENDING 0x02 1415 #define SCB_DMA 0x01 1417 #define SCSICONF 0x5a 1418 #define HWSCSIID 0x0f 1419 #define HSCSIID 0x07 1420 #define TERM_ENB 0x80 1421 #define RESET_SCSI 0x40 1422 #define ENSPCHK 0x20 1426 #define EDGE_TRIG 0x80 1428 #define HOSTCONF 0x5d 1430 #define HA_274_BIOSCTRL 0x5f 1431 #define BIOSDISABLED 0x30 1432 #define BIOSMODE 0x30 1433 #define CHANNEL_B_PRIMARY 0x08 1436 #define PERRORDIS 0x80 1437 #define PAUSEDIS 0x40 1438 #define FAILDIS 0x20 1439 #define FASTMODE 0x10 1440 #define BRKADRINTEN 0x08 1442 #define SEQRESET 0x02 1443 #define LOADRAM 0x01 1447 #define SEQADDR0 0x62 1449 #define SEQADDR1 0x63 1450 #define SEQADDR1_MASK 0x01 1458 #define ALLONES 0x69 1462 #define ALLZEROS 0x6a 1472 #define FUNCTION1 0x6e 1476 #define TARG_OFFSET 0x70 1478 #define SRAM_BASE 0x70 1484 #define DSCOMMAND0 0x84 1485 #define CACHETHEN 0x80 1486 #define DPARCKEN 0x40 1487 #define MPARCKEN 0x20 1488 #define EXTREQLCK 0x10 1489 #define INTSCBRAMSEL 0x08 1491 #define USCBSIZE32 0x02 1492 #define CIOPARCKEN 0x01 1494 #define BUSTIME 0x85 1498 #define DSCOMMAND1 0x85 1500 #define HADDLDSEL1 0x02 1501 #define HADDLDSEL0 0x01 1504 #define DFTHRSH 0xc0 1505 #define DFTHRSH_75 0x80 1509 #define DSPCISTATUS 0x86 1510 #define DFTHRSH_100 0xc0 1512 #define HS_MAILBOX 0x86 1513 #define HOST_MAILBOX 0xf0 1514 #define HOST_TQINPOS 0x80 1515 #define SEQ_MAILBOX 0x0f 1523 #define CHIPRST 0x01 1524 #define CHIPRSTACK 0x01 1532 #define INTSTAT 0x91 1533 #define SEQINT_MASK 0xf1 1534 #define OUT_OF_RANGE 0xe1 1535 #define NO_FREE_SCB 0xd1 1536 #define SCB_MISMATCH 0xc1 1537 #define MISSED_BUSFREE 0xb1 1538 #define MKMSG_FAILED 0xa1 1539 #define DATA_OVERRUN 0x91 1540 #define PERR_DETECTED 0x81 1541 #define BAD_STATUS 0x71 1542 #define HOST_MSG_LOOP 0x61 1543 #define PDATA_REINIT 0x51 1544 #define IGN_WIDE_RES 0x41 1545 #define NO_MATCH 0x31 1546 #define PROTO_VIOLATION 0x21 1547 #define SEND_REJECT 0x11 1548 #define INT_PEND 0x0f 1549 #define BAD_PHASE 0x01 1550 #define BRKADRINT 0x08 1551 #define SCSIINT 0x04 1552 #define CMDCMPLT 0x02 1556 #define CIOPARERR 0x80 1557 #define PCIERRSTAT 0x40 1558 #define MPARERR 0x20 1559 #define DPARERR 0x10 1560 #define SQPARERR 0x08 1561 #define ILLOPCODE 0x04 1562 #define ILLSADDR 0x02 1563 #define ILLHADDR 0x01 1566 #define CLRPARERR 0x10 1567 #define CLRBRKADRINT 0x08 1568 #define CLRSCSIINT 0x04 1569 #define CLRCMDINT 0x02 1570 #define CLRSEQINT 0x01 1572 #define DFCNTRL 0x93 1574 #define DFSTATUS 0x94 1575 #define PRELOAD_AVAIL 0x80 1576 #define DFCACHETH 0x40 1577 #define FIFOQWDEMP 0x20 1578 #define MREQPEND 0x10 1580 #define DFTHRESH 0x04 1581 #define FIFOFULL 0x02 1582 #define FIFOEMP 0x01 1584 #define DFWADDR 0x95 1586 #define DFRADDR 0x97 1591 #define SCBCNT_MASK 0x1f 1592 #define SCBAUTO 0x80 1594 #define QINFIFO 0x9b 1598 #define CRCCONTROL1 0x9d 1599 #define CRCONSEEN 0x80 1600 #define CRCVALCHKEN 0x40 1601 #define CRCENDCHKEN 0x20 1602 #define CRCREQCHKEN 0x10 1603 #define TARGCRCENDEN 0x08 1604 #define TARGCRCCNTEN 0x04 1606 #define QOUTFIFO 0x9d 1608 #define SCSIPHASE 0x9e 1609 #define DATA_PHASE_MASK 0x03 1610 #define STATUS_PHASE 0x20 1611 #define COMMAND_PHASE 0x10 1612 #define MSG_IN_PHASE 0x08 1613 #define MSG_OUT_PHASE 0x04 1614 #define DATA_IN_PHASE 0x02 1615 #define DATA_OUT_PHASE 0x01 1617 #define QOUTCNT 0x9e 1620 #define ALT_MODE 0x80 1622 #define SCB_BASE 0xa0 1624 #define SCB_CDB_PTR 0xa0 1625 #define SCB_CDB_STORE 0xa0 1626 #define SCB_RESIDUAL_DATACNT 0xa0 1628 #define SCB_RESIDUAL_SGPTR 0xa4 1630 #define SCB_SCSI_STATUS 0xa8 1632 #define SCB_TARGET_PHASES 0xa9 1634 #define SCB_TARGET_DATA_DIR 0xaa 1636 #define SCB_TARGET_ITAG 0xab 1638 #define SCB_DATAPTR 0xac 1640 #define SCB_DATACNT 0xb0 1641 #define SG_HIGH_ADDR_BITS 0x7f 1642 #define SG_LAST_SEG 0x80 1644 #define SCB_SGPTR 0xb4 1645 #define SG_RESID_VALID 0x04 1646 #define SG_FULL_RESID 0x02 1647 #define SG_LIST_NULL 0x01 1649 #define SCB_CONTROL 0xb8 1650 #define SCB_TAG_TYPE 0x03 1651 #define TARGET_SCB 0x80 1652 #define STATUS_RCVD 0x80 1653 #define DISCENB 0x40 1654 #define TAG_ENB 0x20 1655 #define MK_MESSAGE 0x10 1656 #define ULTRAENB 0x08 1657 #define DISCONNECTED 0x04 1659 #define SCB_SCSIID 0xb9 1661 #define TWIN_TID 0x70 1663 #define TWIN_CHNLB 0x80 1665 #define SCB_LUN 0xba 1668 #define SCB_TAG 0xbb 1670 #define SCB_CDB_LEN 0xbc 1672 #define SCB_SCSIRATE 0xbd 1674 #define SCB_SCSIOFFSET 0xbe 1676 #define SCB_NEXT 0xbf 1678 #define SCB_64_SPARE 0xc0 1680 #define SEECTL_2840 0xc0 1681 #define CS_2840 0x04 1682 #define CK_2840 0x02 1683 #define DO_2840 0x01 1685 #define STATUS_2840 0xc1 1686 #define BIOS_SEL 0x60 1688 #define EEPROM_TF 0x80 1689 #define DI_2840 0x01 1691 #define SCB_64_BTT 0xd0 1693 #define CCHADDR 0xe0 1697 #define CCSGRAM 0xe9 1699 #define CCSGADDR 0xea 1701 #define CCSGCTL 0xeb 1702 #define CCSGDONE 0x80 1704 #define SG_FETCH_NEEDED 0x02 1705 #define CCSGRESET 0x01 1707 #define CCSCBRAM 0xec 1709 #define CCSCBADDR 0xed 1711 #define CCSCBCTL 0xee 1712 #define CCSCBDONE 0x80 1713 #define ARRDONE 0x40 1714 #define CCARREN 0x10 1715 #define CCSCBEN 0x08 1716 #define CCSCBDIR 0x04 1717 #define CCSCBRESET 0x01 1719 #define CCSCBCNT 0xef 1721 #define SCBBADDR 0xf0 1723 #define CCSCBPTR 0xf1 1725 #define HNSCB_QOFF 0xf4 1727 #define SNSCB_QOFF 0xf6 1729 #define SDSCB_QOFF 0xf8 1731 #define QOFF_CTLSTA 0xfa 1732 #define SCB_QSIZE 0x07 1733 #define SCB_QSIZE_256 0x06 1734 #define SCB_AVAIL 0x40 1735 #define SNSCB_ROLLOVER 0x20 1736 #define SDSCB_ROLLOVER 0x10 1738 #define DFF_THRSH 0xfb 1739 #define WR_DFTHRSH 0x70 1740 #define WR_DFTHRSH_MAX 0x70 1741 #define WR_DFTHRSH_90 0x60 1742 #define WR_DFTHRSH_85 0x50 1743 #define WR_DFTHRSH_75 0x40 1744 #define WR_DFTHRSH_63 0x30 1745 #define WR_DFTHRSH_50 0x20 1746 #define WR_DFTHRSH_25 0x10 1747 #define RD_DFTHRSH_MAX 0x07 1748 #define RD_DFTHRSH 0x07 1749 #define RD_DFTHRSH_90 0x06 1750 #define RD_DFTHRSH_85 0x05 1751 #define RD_DFTHRSH_75 0x04 1752 #define RD_DFTHRSH_63 0x03 1753 #define RD_DFTHRSH_50 0x02 1754 #define RD_DFTHRSH_25 0x01 1755 #define WR_DFTHRSH_MIN 0x00 1756 #define RD_DFTHRSH_MIN 0x00 1758 #define SG_CACHE_SHADOW 0xfc 1759 #define SG_ADDR_MASK 0xf8 1760 #define ODD_SEG 0x04 1761 #define LAST_SEG 0x02 1762 #define LAST_SEG_DONE 0x01 1764 #define SG_CACHE_PRE 0xfc 1767 #define TARGET_DATA_IN 0x01 1768 #define STATUS_BUSY 0x08 1769 #define BUS_16_BIT 0x01 1770 #define TID_SHIFT 0x04 1771 #define SCB_UPLOAD_SIZE 0x20 1772 #define HOST_MAILBOX_SHIFT 0x04 1773 #define MAX_OFFSET_ULTRA2 0x7f 1774 #define SCB_LIST_NULL 0xff 1775 #define HOST_MSG 0xff 1776 #define MAX_OFFSET 0xff 1777 #define BUS_32_BIT 0x02 1778 #define CMD_GROUP_CODE_SHIFT 0x05 1779 #define BUS_8_BIT 0x00 1780 #define CCSGRAM_MAXSEGS 0x10 1781 #define STATUS_QUEUE_FULL 0x28 1782 #define MAX_OFFSET_8BIT 0x0f 1783 #define SCB_DOWNLOAD_SIZE_64 0x30 1784 #define MAX_OFFSET_16BIT 0x08 1785 #define TARGET_CMD_CMPLT 0xfe 1786 #define SG_SIZEOF 0x08 1787 #define SCB_DOWNLOAD_SIZE 0x20 1788 #define SEQ_MAILBOX_SHIFT 0x00 1789 #define CCSGADDR_MAX 0x80 1790 #define STACK_SIZE 0x04 1794 #define SG_PREFETCH_CNT 0x04 1795 #define SG_PREFETCH_ADDR_MASK 0x06 1796 #define SG_PREFETCH_ALIGN_MASK 0x05 1797 #define QOUTFIFO_OFFSET 0x00 1798 #define INVERTED_CACHESIZE_MASK 0x03 1799 #define CACHESIZE_MASK 0x02 1800 #define QINFIFO_OFFSET 0x01 1801 #define DOWNLOAD_CONST_COUNT 0x07 #define ahc_scsiseq_print(regvalue, cur_col, wrap)
#define ahc_seqram_print(regvalue, cur_col, wrap)
#define ahc_sg_cache_shadow_print(regvalue, cur_col, wrap)
#define ahc_scsibusl_print(regvalue, cur_col, wrap)
#define ahc_busy_targets_print(regvalue, cur_col, wrap)
#define ahc_sstat3_print(regvalue, cur_col, wrap)
#define ahc_lastphase_print(regvalue, cur_col, wrap)
#define ahc_seltimer_print(regvalue, cur_col, wrap)
#define ahc_spiocap_print(regvalue, cur_col, wrap)
#define ahc_kernel_qinpos_print(regvalue, cur_col, wrap)
#define ahc_scbcnt_print(regvalue, cur_col, wrap)
#define ahc_scsiphase_print(regvalue, cur_col, wrap)
#define ahc_scsiid_print(regvalue, cur_col, wrap)
#define ahc_cchaddr_print(regvalue, cur_col, wrap)
#define ahc_saved_lun_print(regvalue, cur_col, wrap)
#define ahc_qoutpos_print(regvalue, cur_col, wrap)
#define ahc_scbbaddr_print(regvalue, cur_col, wrap)
#define ahc_status_2840_print(regvalue, cur_col, wrap)
#define ahc_none_print(regvalue, cur_col, wrap)
#define ahc_ccscbcnt_print(regvalue, cur_col, wrap)
#define ahc_scb_next_print(regvalue, cur_col, wrap)
#define ahc_scsiid_ultra2_print(regvalue, cur_col, wrap)
#define ahc_qincnt_print(regvalue, cur_col, wrap)
#define ahc_qoutfifo_print(regvalue, cur_col, wrap)
#define ahc_optionmode_print(regvalue, cur_col, wrap)
#define ahc_targ_offset_print(regvalue, cur_col, wrap)
#define ahc_sxfrctl1_print(regvalue, cur_col, wrap)
#define ahc_scb_lun_print(regvalue, cur_col, wrap)
#define ahc_data_count_odd_print(regvalue, cur_col, wrap)
#define ahc_sindir_print(regvalue, cur_col, wrap)
#define ahc_scb_64_spare_print(regvalue, cur_col, wrap)
#define ahc_next_queued_scb_print(regvalue, cur_col, wrap)
#define ahc_scamctl_print(regvalue, cur_col, wrap)
#define ahc_arg_1_print(regvalue, cur_col, wrap)
#define ahc_dscommand1_print(regvalue, cur_col, wrap)
#define ahc_scsisigi_print(regvalue, cur_col, wrap)
#define ahc_cchcnt_print(regvalue, cur_col, wrap)
#define ahc_dfdat_print(regvalue, cur_col, wrap)
#define ahc_ccscbptr_print(regvalue, cur_col, wrap)
#define ahc_qinfifo_print(regvalue, cur_col, wrap)
#define ahc_ha_274_biosctrl_print(regvalue, cur_col, wrap)
#define ahc_stack_print(regvalue, cur_col, wrap)
#define ahc_busspd_print(regvalue, cur_col, wrap)
#define ahc_bustime_print(regvalue, cur_col, wrap)
#define ahc_seqctl_print(regvalue, cur_col, wrap)
#define ahc_sg_cache_pre_print(regvalue, cur_col, wrap)
#define ahc_intstat_print(regvalue, cur_col, wrap)
#define ahc_allones_print(regvalue, cur_col, wrap)
#define ahc_scsidatl_print(regvalue, cur_col, wrap)
#define ahc_bctl_print(regvalue, cur_col, wrap)
#define ahc_disc_dsb_print(regvalue, cur_col, wrap)
#define ahc_tqinpos_print(regvalue, cur_col, wrap)
#define ahc_free_scbh_print(regvalue, cur_col, wrap)
#define ahc_ccscbram_print(regvalue, cur_col, wrap)
#define ahc_seq_flags2_print(regvalue, cur_col, wrap)
#define ahc_sxfrctl2_print(regvalue, cur_col, wrap)
#define ahc_scb_tag_print(regvalue, cur_col, wrap)
#define ahc_scsiconf_print(regvalue, cur_col, wrap)
#define ahc_sindex_print(regvalue, cur_col, wrap)
#define ahc_arg_2_print(regvalue, cur_col, wrap)
#define ahc_seectl_print(regvalue, cur_col, wrap)
#define ahc_sstat0_print(regvalue, cur_col, wrap)
#define ahc_hscb_addr_print(regvalue, cur_col, wrap)
#define ahc_ccsgram_print(regvalue, cur_col, wrap)
#define ahc_scb_scsirate_print(regvalue, cur_col, wrap)
#define ahc_hostconf_print(regvalue, cur_col, wrap)
#define ahc_selid_print(regvalue, cur_col, wrap)
#define ahc_mwi_residual_print(regvalue, cur_col, wrap)
#define ahc_seq_flags_print(regvalue, cur_col, wrap)
#define ahc_scb_base_print(regvalue, cur_col, wrap)
#define ahc_ccsgaddr_print(regvalue, cur_col, wrap)
#define ahc_sblkctl_print(regvalue, cur_col, wrap)
#define ahc_seectl_2840_print(regvalue, cur_col, wrap)
#define ahc_allzeros_print(regvalue, cur_col, wrap)
#define ahc_dindex_print(regvalue, cur_col, wrap)
#define ahc_brdctl_print(regvalue, cur_col, wrap)
#define ahc_error_print(regvalue, cur_col, wrap)
#define ahc_haddr_print(regvalue, cur_col, wrap)
#define ahc_scsidath_print(regvalue, cur_col, wrap)
#define ahc_scb_scsi_status_print(regvalue, cur_col, wrap)
#define ahc_sdscb_qoff_print(regvalue, cur_col, wrap)
#define ahc_hnscb_qoff_print(regvalue, cur_col, wrap)
#define ahc_scb_dataptr_print(regvalue, cur_col, wrap)
#define ahc_sstat2_print(regvalue, cur_col, wrap)
#define ahc_targid_print(regvalue, cur_col, wrap)
#define ahc_disconnected_scbh_print(regvalue, cur_col, wrap)
#define ahc_qoutcnt_print(regvalue, cur_col, wrap)
#define ahc_kernel_tqinpos_print(regvalue, cur_col, wrap)
#define ahc_scb_datacnt_print(regvalue, cur_col, wrap)
#define ahc_dfraddr_print(regvalue, cur_col, wrap)
#define ahc_shared_data_addr_print(regvalue, cur_col, wrap)
#define ahc_cmdsize_table_tail_print(regvalue, cur_col, wrap)
#define ahc_scsiseq_template_print(regvalue, cur_col, wrap)
#define ahc_dfwaddr_print(regvalue, cur_col, wrap)
#define ahc_intdef_print(regvalue, cur_col, wrap)
#define ahc_dindir_print(regvalue, cur_col, wrap)
#define ahc_seqaddr1_print(regvalue, cur_col, wrap)
#define ahc_ccsgctl_print(regvalue, cur_col, wrap)
#define ahc_sfunct_print(regvalue, cur_col, wrap)
#define ahc_scb_cdb_len_print(regvalue, cur_col, wrap)
#define ahc_scsirate_print(regvalue, cur_col, wrap)
#define ahc_scsibush_print(regvalue, cur_col, wrap)
#define ahc_sram_base_print(regvalue, cur_col, wrap)
#define ahc_saved_scsiid_print(regvalue, cur_col, wrap)
#define ahc_dspcistatus_print(regvalue, cur_col, wrap)
#define ahc_ccscbaddr_print(regvalue, cur_col, wrap)
#define ahc_scb_scsioffset_print(regvalue, cur_col, wrap)
#define ahc_targcrccnt_print(regvalue, cur_col, wrap)
#define ahc_last_msg_print(regvalue, cur_col, wrap)
#define ahc_seqaddr0_print(regvalue, cur_col, wrap)
#define ahc_scb_residual_sgptr_print(regvalue, cur_col, wrap)
#define ahc_scb_scsiid_print(regvalue, cur_col, wrap)
#define ahc_shaddr_print(regvalue, cur_col, wrap)
#define ahc_hcnt_print(regvalue, cur_col, wrap)
#define ahc_ultra_enb_print(regvalue, cur_col, wrap)
#define ahc_dmaparams_print(regvalue, cur_col, wrap)
#define ahc_clrsint1_print(regvalue, cur_col, wrap)
#define ahc_flags_print(regvalue, cur_col, wrap)
#define ahc_dscommand0_print(regvalue, cur_col, wrap)
#define ahc_snscb_qoff_print(regvalue, cur_col, wrap)
#define ahc_crccontrol1_print(regvalue, cur_col, wrap)
#define ahc_dfcntrl_print(regvalue, cur_col, wrap)
#define ahc_complete_scbh_print(regvalue, cur_col, wrap)
#define ahc_simode0_print(regvalue, cur_col, wrap)
#define ahc_qinpos_print(regvalue, cur_col, wrap)
#define ahc_clrsint0_print(regvalue, cur_col, wrap)
#define ahc_waiting_scbh_print(regvalue, cur_col, wrap)
#define ahc_scbptr_print(regvalue, cur_col, wrap)
#define ahc_accum_print(regvalue, cur_col, wrap)
#define ahc_scb_64_btt_print(regvalue, cur_col, wrap)
#define ahc_scb_target_phases_print(regvalue, cur_col, wrap)
#define ahc_scb_control_print(regvalue, cur_col, wrap)
#define ahc_qoff_ctlsta_print(regvalue, cur_col, wrap)
#define ahc_sstat1_print(regvalue, cur_col, wrap)
#define ahc_dfstatus_print(regvalue, cur_col, wrap)
#define ahc_simode1_print(regvalue, cur_col, wrap)
#define ahc_scsisigo_print(regvalue, cur_col, wrap)
#define ahc_stcnt_print(regvalue, cur_col, wrap)
#define ahc_hs_mailbox_print(regvalue, cur_col, wrap)
#define ahc_sxfrctl0_print(regvalue, cur_col, wrap)
#define ahc_msg_out_print(regvalue, cur_col, wrap)
#define ahc_scb_target_data_dir_print(regvalue, cur_col, wrap)
#define ahc_clrint_print(regvalue, cur_col, wrap)
#define ahc_hcntrl_print(regvalue, cur_col, wrap)
#define ahc_ha_274_biosglobal_print(regvalue, cur_col, wrap)
#define ahc_scb_target_itag_print(regvalue, cur_col, wrap)
#define ahc_scb_cdb_ptr_print(regvalue, cur_col, wrap)
#define ahc_function1_print(regvalue, cur_col, wrap)
#define ahc_ccscbctl_print(regvalue, cur_col, wrap)
#define ahc_scb_sgptr_print(regvalue, cur_col, wrap)
#define ahc_dff_thrsh_print(regvalue, cur_col, wrap)