mii.h File Reference

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mii.h File Reference

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Macros

#define MII_NPHY   32 /* max # of PHYs per MII */
 
#define MII_ADDRBITS   5 /* Register address bits (0x00..0x1f) */
 
#define MII_ADDRMASK   0x1f /* Address mask */
 
#define MII_COMMAND_START   0x01
 
#define MII_COMMAND_READ   0x02
 
#define MII_COMMAND_WRITE   0x01
 
#define MII_COMMAND_ACK   0x02
 
#define MII_BMCR   0x00 /* Basic mode control register (rw) */
 
#define BMCR_RESET   0x8000 /* reset */
 
#define BMCR_LOOP   0x4000 /* loopback */
 
#define BMCR_SPEED0   0x2000 /* speed selection (LSB) */
 
#define BMCR_AUTOEN   0x1000 /* autonegotiation enable */
 
#define BMCR_PDOWN   0x0800 /* power down */
 
#define BMCR_ISO   0x0400 /* isolate */
 
#define BMCR_STARTNEG   0x0200 /* restart autonegotiation */
 
#define BMCR_FDX   0x0100 /* Set duplex mode */
 
#define BMCR_CTEST   0x0080 /* collision test */
 
#define BMCR_SPEED1   0x0040 /* speed selection (MSB) */
 
#define BMCR_S10   0x0000 /* 10 Mb/s */
 
#define BMCR_S100   BMCR_SPEED0 /* 100 Mb/s */
 
#define BMCR_S1000   BMCR_SPEED1 /* 1000 Mb/s */
 
#define BMCR_SPEED(x)   ((x) & (BMCR_SPEED0|BMCR_SPEED1))
 
#define MII_BMSR   0x01 /* Basic mode status register (ro) */
 
#define BMSR_100T4   0x8000 /* 100 base T4 capable */
 
#define BMSR_100TXFDX   0x4000 /* 100 base Tx full duplex capable */
 
#define BMSR_100TXHDX   0x2000 /* 100 base Tx half duplex capable */
 
#define BMSR_10TFDX   0x1000 /* 10 base T full duplex capable */
 
#define BMSR_10THDX   0x0800 /* 10 base T half duplex capable */
 
#define BMSR_100T2FDX   0x0400 /* 100 base T2 full duplex capable */
 
#define BMSR_100T2HDX   0x0200 /* 100 base T2 half duplex capable */
 
#define BMSR_EXTSTAT   0x0100 /* Extended status in register 15 */
 
#define BMSR_MFPS   0x0040 /* MII Frame Preamble Suppression */
 
#define BMSR_ACOMP   0x0020 /* Autonegotiation complete */
 
#define BMSR_RFAULT   0x0010 /* Link partner fault */
 
#define BMSR_ANEG   0x0008 /* Autonegotiation capable */
 
#define BMSR_LINK   0x0004 /* Link status */
 
#define BMSR_JABBER   0x0002 /* Jabber detected */
 
#define BMSR_EXTCAP   0x0001 /* Extended capability */
 
#define BMSR_MEDIAMASK
 
#define BMSR_MEDIA_TO_ANAR(x)   (((x) & BMSR_MEDIAMASK) >> 6)
 
#define MII_PHYIDR1   0x02 /* ID register 1 (ro) */
 
#define MII_PHYIDR2   0x03 /* ID register 2 (ro) */
 
#define IDR2_OUILSB   0xfc00 /* OUI LSB */
 
#define IDR2_MODEL   0x03f0 /* vendor model */
 
#define IDR2_REV   0x000f /* vendor revision */
 
#define MII_ANAR   0x04 /* Autonegotiation advertisement (rw) */
 
#define ANAR_NP   0x8000 /* Next page (ro) */
 
#define ANAR_ACK   0x4000 /* link partner abilities acknowledged (ro) */
 
#define ANAR_RF   0x2000 /* remote fault (ro) */
 
#define ANAR_FC   0x0400 /* local device supports PAUSE */
 
#define ANAR_T4   0x0200 /* local device supports 100bT4 */
 
#define ANAR_TX_FD   0x0100 /* local device supports 100bTx FD */
 
#define ANAR_TX   0x0080 /* local device supports 100bTx */
 
#define ANAR_10_FD   0x0040 /* local device supports 10bT FD */
 
#define ANAR_10   0x0020 /* local device supports 10bT */
 
#define ANAR_CSMA   0x0001 /* protocol selector CSMA/CD */
 
#define ANAR_PAUSE_NONE   (0 << 10)
 
#define ANAR_PAUSE_SYM   (1 << 10)
 
#define ANAR_PAUSE_ASYM   (2 << 10)
 
#define ANAR_PAUSE_TOWARDS   (3 << 10)
 
#define ANAR_X_FD   0x0020 /* local device supports 1000BASE-X FD */
 
#define ANAR_X_HD   0x0040 /* local device supports 1000BASE-X HD */
 
#define ANAR_X_PAUSE_NONE   (0 << 7)
 
#define ANAR_X_PAUSE_SYM   (1 << 7)
 
#define ANAR_X_PAUSE_ASYM   (2 << 7)
 
#define ANAR_X_PAUSE_TOWARDS   (3 << 7)
 
#define MII_ANLPAR   0x05 /* Autonegotiation lnk partner abilities (rw) */
 
#define ANLPAR_NP   0x8000 /* Next page (ro) */
 
#define ANLPAR_ACK   0x4000 /* link partner accepted ACK (ro) */
 
#define ANLPAR_RF   0x2000 /* remote fault (ro) */
 
#define ANLPAR_FC   0x0400 /* link partner supports PAUSE */
 
#define ANLPAR_T4   0x0200 /* link partner supports 100bT4 */
 
#define ANLPAR_TX_FD   0x0100 /* link partner supports 100bTx FD */
 
#define ANLPAR_TX   0x0080 /* link partner supports 100bTx */
 
#define ANLPAR_10_FD   0x0040 /* link partner supports 10bT FD */
 
#define ANLPAR_10   0x0020 /* link partner supports 10bT */
 
#define ANLPAR_CSMA   0x0001 /* protocol selector CSMA/CD */
 
#define ANLPAR_PAUSE_MASK   (3 << 10)
 
#define ANLPAR_PAUSE_NONE   (0 << 10)
 
#define ANLPAR_PAUSE_SYM   (1 << 10)
 
#define ANLPAR_PAUSE_ASYM   (2 << 10)
 
#define ANLPAR_PAUSE_TOWARDS   (3 << 10)
 
#define ANLPAR_X_FD   0x0020 /* local device supports 1000BASE-X FD */
 
#define ANLPAR_X_HD   0x0040 /* local device supports 1000BASE-X HD */
 
#define ANLPAR_X_PAUSE_MASK   (3 << 7)
 
#define ANLPAR_X_PAUSE_NONE   (0 << 7)
 
#define ANLPAR_X_PAUSE_SYM   (1 << 7)
 
#define ANLPAR_X_PAUSE_ASYM   (2 << 7)
 
#define ANLPAR_X_PAUSE_TOWARDS   (3 << 7)
 
#define MII_ANER   0x06 /* Autonegotiation expansion (ro) */
 
#define ANER_MLF   0x0010 /* multiple link detection fault */
 
#define ANER_LPNP   0x0008 /* link parter next page-able */
 
#define ANER_NP   0x0004 /* next page-able */
 
#define ANER_PAGE_RX   0x0002 /* Page received */
 
#define ANER_LPAN   0x0001 /* link parter autoneg-able */
 
#define MII_ANNP   0x07 /* Autonegotiation next page */
 
#define MII_ANLPRNP   0x08 /* Autonegotiation link partner rx next page */
 
#define MII_100T2CR   0x09 /* 100base-T2 control register */
 
#define GTCR_TEST_MASK   0xe000 /* see 802.3ab ss. 40.6.1.1.2 */
 
#define GTCR_MAN_MS   0x1000 /* enable manual master/slave control */
 
#define GTCR_ADV_MS   0x0800 /* 1 = adv. master, 0 = adv. slave */
 
#define GTCR_PORT_TYPE   0x0400 /* 1 = DCE, 0 = DTE (NIC) */
 
#define GTCR_ADV_1000TFDX   0x0200 /* adv. 1000baseT FDX */
 
#define GTCR_ADV_1000THDX   0x0100 /* adv. 1000baseT HDX */
 
#define MII_100T2SR   0x0a /* 100base-T2 status register */
 
#define GTSR_MAN_MS_FLT   0x8000 /* master/slave config fault */
 
#define GTSR_MS_RES   0x4000 /* result: 1 = master, 0 = slave */
 
#define GTSR_LRS   0x2000 /* local rx status, 1 = ok */
 
#define GTSR_RRS   0x1000 /* remote rx status, 1 = ok */
 
#define GTSR_LP_1000TFDX   0x0800 /* link partner 1000baseT FDX capable */
 
#define GTSR_LP_1000THDX   0x0400 /* link partner 1000baseT HDX capable */
 
#define GTSR_LP_ASM_DIR   0x0200 /* link partner asym. pause dir. capable */
 
#define GTSR_IDLE_ERR   0x00ff /* IDLE error count */
 
#define MII_PSECR   0x0b /* PSE control register */
 
#define PSECR_PACTLMASK   0x000c /* pair control mask */
 
#define PSECR_PSEENMASK   0x0003 /* PSE enable mask */
 
#define PSECR_PINOUTB   0x0008 /* PSE pinout Alternative B */
 
#define PSECR_PINOUTA   0x0004 /* PSE pinout Alternative A */
 
#define PSECR_FOPOWTST   0x0002 /* Force Power Test Mode */
 
#define PSECR_PSEEN   0x0001 /* PSE Enabled */
 
#define PSECR_PSEDIS   0x0000 /* PSE Disabled */
 
#define MII_PSESR   0x0c /* PSE status register */
 
#define PSESR_PWRDENIED   0x1000 /* Power Denied */
 
#define PSESR_VALSIG   0x0800 /* Valid PD signature detected */
 
#define PSESR_INVALSIG   0x0400 /* Invalid PD signature detected */
 
#define PSESR_SHORTCIRC   0x0200 /* Short circuit condition detected */
 
#define PSESR_OVERLOAD   0x0100 /* Overload condition detected */
 
#define PSESR_MPSABSENT   0x0080 /* MPS absent condition detected */
 
#define PSESR_PDCLMASK   0x0070 /* PD Class mask */
 
#define PSESR_STATMASK   0x000e /* PSE Status mask */
 
#define PSESR_PAIRCTABL   0x0001 /* PAIR Control Ability */
 
#define PSESR_PDCL_4   (4 << 4) /* Class 4 */
 
#define PSESR_PDCL_3   (3 << 4) /* Class 3 */
 
#define PSESR_PDCL_2   (2 << 4) /* Class 2 */
 
#define PSESR_PDCL_1   (1 << 4) /* Class 1 */
 
#define PSESR_PDCL_0   (0 << 4) /* Class 0 */
 
#define MII_MMDACR   0x0d /* MMD access control register */
 
#define MMDACR_FUNCMASK   0xc000 /* function */
 
#define MMDACR_DADDRMASK   0x001f /* device address */
 
#define MMDACR_FN_ADDRESS   (0 << 14) /* address */
 
#define MMDACR_FN_DATANPI   (1 << 14) /* data, no post increment */
 
#define MMDACR_FN_DATAPIRW   (2 << 14) /* data, post increment on r/w */
 
#define MMDACR_FN_DATAPIW   (3 << 14) /* data, post increment on wr only */
 
#define MII_MMDAADR   0x0e /* MMD access address data register */
 
#define MII_EXTSR   0x0f /* Extended status register */
 
#define EXTSR_1000XFDX   0x8000 /* 1000X full-duplex capable */
 
#define EXTSR_1000XHDX   0x4000 /* 1000X half-duplex capable */
 
#define EXTSR_1000TFDX   0x2000 /* 1000T full-duplex capable */
 
#define EXTSR_1000THDX   0x1000 /* 1000T half-duplex capable */
 
#define EXTSR_MEDIAMASK
 

Macro Definition Documentation

◆ ANAR_10

#define ANAR_10   0x0020 /* local device supports 10bT */

Definition at line 118 of file mii.h.

◆ ANAR_10_FD

#define ANAR_10_FD   0x0040 /* local device supports 10bT FD */

Definition at line 117 of file mii.h.

◆ ANAR_ACK

#define ANAR_ACK   0x4000 /* link partner abilities acknowledged (ro) */

Definition at line 110 of file mii.h.

◆ ANAR_CSMA

#define ANAR_CSMA   0x0001 /* protocol selector CSMA/CD */

Definition at line 119 of file mii.h.

◆ ANAR_FC

#define ANAR_FC   0x0400 /* local device supports PAUSE */

Definition at line 113 of file mii.h.

◆ ANAR_NP

#define ANAR_NP   0x8000 /* Next page (ro) */

Definition at line 109 of file mii.h.

◆ ANAR_PAUSE_ASYM

#define ANAR_PAUSE_ASYM   (2 << 10)

Definition at line 122 of file mii.h.

◆ ANAR_PAUSE_NONE

#define ANAR_PAUSE_NONE   (0 << 10)

Definition at line 120 of file mii.h.

◆ ANAR_PAUSE_SYM

#define ANAR_PAUSE_SYM   (1 << 10)

Definition at line 121 of file mii.h.

◆ ANAR_PAUSE_TOWARDS

#define ANAR_PAUSE_TOWARDS   (3 << 10)

Definition at line 123 of file mii.h.

◆ ANAR_RF

#define ANAR_RF   0x2000 /* remote fault (ro) */

Definition at line 111 of file mii.h.

◆ ANAR_T4

#define ANAR_T4   0x0200 /* local device supports 100bT4 */

Definition at line 114 of file mii.h.

◆ ANAR_TX

#define ANAR_TX   0x0080 /* local device supports 100bTx */

Definition at line 116 of file mii.h.

◆ ANAR_TX_FD

#define ANAR_TX_FD   0x0100 /* local device supports 100bTx FD */

Definition at line 115 of file mii.h.

◆ ANAR_X_FD

#define ANAR_X_FD   0x0020 /* local device supports 1000BASE-X FD */

Definition at line 126 of file mii.h.

◆ ANAR_X_HD

#define ANAR_X_HD   0x0040 /* local device supports 1000BASE-X HD */

Definition at line 127 of file mii.h.

◆ ANAR_X_PAUSE_ASYM

#define ANAR_X_PAUSE_ASYM   (2 << 7)

Definition at line 130 of file mii.h.

◆ ANAR_X_PAUSE_NONE

#define ANAR_X_PAUSE_NONE   (0 << 7)

Definition at line 128 of file mii.h.

◆ ANAR_X_PAUSE_SYM

#define ANAR_X_PAUSE_SYM   (1 << 7)

Definition at line 129 of file mii.h.

◆ ANAR_X_PAUSE_TOWARDS

#define ANAR_X_PAUSE_TOWARDS   (3 << 7)

Definition at line 131 of file mii.h.

◆ ANER_LPAN

#define ANER_LPAN   0x0001 /* link parter autoneg-able */

Definition at line 165 of file mii.h.

◆ ANER_LPNP

#define ANER_LPNP   0x0008 /* link parter next page-able */

Definition at line 162 of file mii.h.

◆ ANER_MLF

#define ANER_MLF   0x0010 /* multiple link detection fault */

Definition at line 161 of file mii.h.

◆ ANER_NP

#define ANER_NP   0x0004 /* next page-able */

Definition at line 163 of file mii.h.

◆ ANER_PAGE_RX

#define ANER_PAGE_RX   0x0002 /* Page received */

Definition at line 164 of file mii.h.

◆ ANLPAR_10

#define ANLPAR_10   0x0020 /* link partner supports 10bT */

Definition at line 143 of file mii.h.

◆ ANLPAR_10_FD

#define ANLPAR_10_FD   0x0040 /* link partner supports 10bT FD */

Definition at line 142 of file mii.h.

◆ ANLPAR_ACK

#define ANLPAR_ACK   0x4000 /* link partner accepted ACK (ro) */

Definition at line 136 of file mii.h.

◆ ANLPAR_CSMA

#define ANLPAR_CSMA   0x0001 /* protocol selector CSMA/CD */

Definition at line 144 of file mii.h.

◆ ANLPAR_FC

#define ANLPAR_FC   0x0400 /* link partner supports PAUSE */

Definition at line 138 of file mii.h.

◆ ANLPAR_NP

#define ANLPAR_NP   0x8000 /* Next page (ro) */

Definition at line 135 of file mii.h.

◆ ANLPAR_PAUSE_ASYM

#define ANLPAR_PAUSE_ASYM   (2 << 10)

Definition at line 148 of file mii.h.

◆ ANLPAR_PAUSE_MASK

#define ANLPAR_PAUSE_MASK   (3 << 10)

Definition at line 145 of file mii.h.

◆ ANLPAR_PAUSE_NONE

#define ANLPAR_PAUSE_NONE   (0 << 10)

Definition at line 146 of file mii.h.

◆ ANLPAR_PAUSE_SYM

#define ANLPAR_PAUSE_SYM   (1 << 10)

Definition at line 147 of file mii.h.

◆ ANLPAR_PAUSE_TOWARDS

#define ANLPAR_PAUSE_TOWARDS   (3 << 10)

Definition at line 149 of file mii.h.

◆ ANLPAR_RF

#define ANLPAR_RF   0x2000 /* remote fault (ro) */

Definition at line 137 of file mii.h.

◆ ANLPAR_T4

#define ANLPAR_T4   0x0200 /* link partner supports 100bT4 */

Definition at line 139 of file mii.h.

◆ ANLPAR_TX

#define ANLPAR_TX   0x0080 /* link partner supports 100bTx */

Definition at line 141 of file mii.h.

◆ ANLPAR_TX_FD

#define ANLPAR_TX_FD   0x0100 /* link partner supports 100bTx FD */

Definition at line 140 of file mii.h.

◆ ANLPAR_X_FD

#define ANLPAR_X_FD   0x0020 /* local device supports 1000BASE-X FD */

Definition at line 151 of file mii.h.

◆ ANLPAR_X_HD

#define ANLPAR_X_HD   0x0040 /* local device supports 1000BASE-X HD */

Definition at line 152 of file mii.h.

◆ ANLPAR_X_PAUSE_ASYM

#define ANLPAR_X_PAUSE_ASYM   (2 << 7)

Definition at line 156 of file mii.h.

◆ ANLPAR_X_PAUSE_MASK

#define ANLPAR_X_PAUSE_MASK   (3 << 7)

Definition at line 153 of file mii.h.

◆ ANLPAR_X_PAUSE_NONE

#define ANLPAR_X_PAUSE_NONE   (0 << 7)

Definition at line 154 of file mii.h.

◆ ANLPAR_X_PAUSE_SYM

#define ANLPAR_X_PAUSE_SYM   (1 << 7)

Definition at line 155 of file mii.h.

◆ ANLPAR_X_PAUSE_TOWARDS

#define ANLPAR_X_PAUSE_TOWARDS   (3 << 7)

Definition at line 157 of file mii.h.

◆ BMCR_AUTOEN

#define BMCR_AUTOEN   0x1000 /* autonegotiation enable */

Definition at line 54 of file mii.h.

◆ BMCR_CTEST

#define BMCR_CTEST   0x0080 /* collision test */

Definition at line 59 of file mii.h.

◆ BMCR_FDX

#define BMCR_FDX   0x0100 /* Set duplex mode */

Definition at line 58 of file mii.h.

◆ BMCR_ISO

#define BMCR_ISO   0x0400 /* isolate */

Definition at line 56 of file mii.h.

◆ BMCR_LOOP

#define BMCR_LOOP   0x4000 /* loopback */

Definition at line 52 of file mii.h.

◆ BMCR_PDOWN

#define BMCR_PDOWN   0x0800 /* power down */

Definition at line 55 of file mii.h.

◆ BMCR_RESET

#define BMCR_RESET   0x8000 /* reset */

Definition at line 51 of file mii.h.

◆ BMCR_S10

#define BMCR_S10   0x0000 /* 10 Mb/s */

Definition at line 62 of file mii.h.

◆ BMCR_S100

#define BMCR_S100   BMCR_SPEED0 /* 100 Mb/s */

Definition at line 63 of file mii.h.

◆ BMCR_S1000

#define BMCR_S1000   BMCR_SPEED1 /* 1000 Mb/s */

Definition at line 64 of file mii.h.

◆ BMCR_SPEED

#define BMCR_SPEED (   x)    ((x) & (BMCR_SPEED0|BMCR_SPEED1))

Definition at line 66 of file mii.h.

◆ BMCR_SPEED0

#define BMCR_SPEED0   0x2000 /* speed selection (LSB) */

Definition at line 53 of file mii.h.

◆ BMCR_SPEED1

#define BMCR_SPEED1   0x0040 /* speed selection (MSB) */

Definition at line 60 of file mii.h.

◆ BMCR_STARTNEG

#define BMCR_STARTNEG   0x0200 /* restart autonegotiation */

Definition at line 57 of file mii.h.

◆ BMSR_100T2FDX

#define BMSR_100T2FDX   0x0400 /* 100 base T2 full duplex capable */

Definition at line 74 of file mii.h.

◆ BMSR_100T2HDX

#define BMSR_100T2HDX   0x0200 /* 100 base T2 half duplex capable */

Definition at line 75 of file mii.h.

◆ BMSR_100T4

#define BMSR_100T4   0x8000 /* 100 base T4 capable */

Definition at line 69 of file mii.h.

◆ BMSR_100TXFDX

#define BMSR_100TXFDX   0x4000 /* 100 base Tx full duplex capable */

Definition at line 70 of file mii.h.

◆ BMSR_100TXHDX

#define BMSR_100TXHDX   0x2000 /* 100 base Tx half duplex capable */

Definition at line 71 of file mii.h.

◆ BMSR_10TFDX

#define BMSR_10TFDX   0x1000 /* 10 base T full duplex capable */

Definition at line 72 of file mii.h.

◆ BMSR_10THDX

#define BMSR_10THDX   0x0800 /* 10 base T half duplex capable */

Definition at line 73 of file mii.h.

◆ BMSR_ACOMP

#define BMSR_ACOMP   0x0020 /* Autonegotiation complete */

Definition at line 78 of file mii.h.

◆ BMSR_ANEG

#define BMSR_ANEG   0x0008 /* Autonegotiation capable */

Definition at line 80 of file mii.h.

◆ BMSR_EXTCAP

#define BMSR_EXTCAP   0x0001 /* Extended capability */

Definition at line 83 of file mii.h.

◆ BMSR_EXTSTAT

#define BMSR_EXTSTAT   0x0100 /* Extended status in register 15 */

Definition at line 76 of file mii.h.

◆ BMSR_JABBER

#define BMSR_JABBER   0x0002 /* Jabber detected */

Definition at line 82 of file mii.h.

◆ BMSR_LINK

#define BMSR_LINK   0x0004 /* Link status */

Definition at line 81 of file mii.h.

◆ BMSR_MEDIA_TO_ANAR

#define BMSR_MEDIA_TO_ANAR (   x)    (((x) & BMSR_MEDIAMASK) >> 6)

Definition at line 98 of file mii.h.

◆ BMSR_MEDIAMASK

#define BMSR_MEDIAMASK
Value:
#define BMSR_100T2FDX
Definition: mii.h:74
#define BMSR_100TXFDX
Definition: mii.h:70
#define BMSR_100TXHDX
Definition: mii.h:71
#define BMSR_10THDX
Definition: mii.h:73
#define BMSR_100T4
Definition: mii.h:69
#define BMSR_100T2HDX
Definition: mii.h:75

Definition at line 91 of file mii.h.

◆ BMSR_MFPS

#define BMSR_MFPS   0x0040 /* MII Frame Preamble Suppression */

Definition at line 77 of file mii.h.

◆ BMSR_RFAULT

#define BMSR_RFAULT   0x0010 /* Link partner fault */

Definition at line 79 of file mii.h.

◆ EXTSR_1000TFDX

#define EXTSR_1000TFDX   0x2000 /* 1000T full-duplex capable */

Definition at line 231 of file mii.h.

◆ EXTSR_1000THDX

#define EXTSR_1000THDX   0x1000 /* 1000T half-duplex capable */

Definition at line 232 of file mii.h.

◆ EXTSR_1000XFDX

#define EXTSR_1000XFDX   0x8000 /* 1000X full-duplex capable */

Definition at line 229 of file mii.h.

◆ EXTSR_1000XHDX

#define EXTSR_1000XHDX   0x4000 /* 1000X half-duplex capable */

Definition at line 230 of file mii.h.

◆ EXTSR_MEDIAMASK

#define EXTSR_MEDIAMASK
Value:
EXTSR_1000TFDX|EXTSR_1000THDX)
#define EXTSR_1000THDX
Definition: mii.h:232
#define EXTSR_1000XHDX
Definition: mii.h:230
#define EXTSR_1000XFDX
Definition: mii.h:229

Definition at line 234 of file mii.h.

◆ GTCR_ADV_1000TFDX

#define GTCR_ADV_1000TFDX   0x0200 /* adv. 1000baseT FDX */

Definition at line 179 of file mii.h.

◆ GTCR_ADV_1000THDX

#define GTCR_ADV_1000THDX   0x0100 /* adv. 1000baseT HDX */

Definition at line 180 of file mii.h.

◆ GTCR_ADV_MS

#define GTCR_ADV_MS   0x0800 /* 1 = adv. master, 0 = adv. slave */

Definition at line 177 of file mii.h.

◆ GTCR_MAN_MS

#define GTCR_MAN_MS   0x1000 /* enable manual master/slave control */

Definition at line 176 of file mii.h.

◆ GTCR_PORT_TYPE

#define GTCR_PORT_TYPE   0x0400 /* 1 = DCE, 0 = DTE (NIC) */

Definition at line 178 of file mii.h.

◆ GTCR_TEST_MASK

#define GTCR_TEST_MASK   0xe000 /* see 802.3ab ss. 40.6.1.1.2 */

Definition at line 175 of file mii.h.

◆ GTSR_IDLE_ERR

#define GTSR_IDLE_ERR   0x00ff /* IDLE error count */

Definition at line 191 of file mii.h.

◆ GTSR_LP_1000TFDX

#define GTSR_LP_1000TFDX   0x0800 /* link partner 1000baseT FDX capable */

Definition at line 188 of file mii.h.

◆ GTSR_LP_1000THDX

#define GTSR_LP_1000THDX   0x0400 /* link partner 1000baseT HDX capable */

Definition at line 189 of file mii.h.

◆ GTSR_LP_ASM_DIR

#define GTSR_LP_ASM_DIR   0x0200 /* link partner asym. pause dir. capable */

Definition at line 190 of file mii.h.

◆ GTSR_LRS

#define GTSR_LRS   0x2000 /* local rx status, 1 = ok */

Definition at line 186 of file mii.h.

◆ GTSR_MAN_MS_FLT

#define GTSR_MAN_MS_FLT   0x8000 /* master/slave config fault */

Definition at line 184 of file mii.h.

◆ GTSR_MS_RES

#define GTSR_MS_RES   0x4000 /* result: 1 = master, 0 = slave */

Definition at line 185 of file mii.h.

◆ GTSR_RRS

#define GTSR_RRS   0x1000 /* remote rx status, 1 = ok */

Definition at line 187 of file mii.h.

◆ IDR2_MODEL

#define IDR2_MODEL   0x03f0 /* vendor model */

Definition at line 104 of file mii.h.

◆ IDR2_OUILSB

#define IDR2_OUILSB   0xfc00 /* OUI LSB */

Definition at line 103 of file mii.h.

◆ IDR2_REV

#define IDR2_REV   0x000f /* vendor revision */

Definition at line 105 of file mii.h.

◆ MII_100T2CR

#define MII_100T2CR   0x09 /* 100base-T2 control register */

Definition at line 174 of file mii.h.

◆ MII_100T2SR

#define MII_100T2SR   0x0a /* 100base-T2 status register */

Definition at line 183 of file mii.h.

◆ MII_ADDRBITS

#define MII_ADDRBITS   5 /* Register address bits (0x00..0x1f) */

Definition at line 38 of file mii.h.

◆ MII_ADDRMASK

#define MII_ADDRMASK   0x1f /* Address mask */

Definition at line 39 of file mii.h.

◆ MII_ANAR

#define MII_ANAR   0x04 /* Autonegotiation advertisement (rw) */

Definition at line 107 of file mii.h.

◆ MII_ANER

#define MII_ANER   0x06 /* Autonegotiation expansion (ro) */

Definition at line 159 of file mii.h.

◆ MII_ANLPAR

#define MII_ANLPAR   0x05 /* Autonegotiation lnk partner abilities (rw) */

Definition at line 133 of file mii.h.

◆ MII_ANLPRNP

#define MII_ANLPRNP   0x08 /* Autonegotiation link partner rx next page */

Definition at line 170 of file mii.h.

◆ MII_ANNP

#define MII_ANNP   0x07 /* Autonegotiation next page */

Definition at line 167 of file mii.h.

◆ MII_BMCR

#define MII_BMCR   0x00 /* Basic mode control register (rw) */

Definition at line 50 of file mii.h.

◆ MII_BMSR

#define MII_BMSR   0x01 /* Basic mode status register (ro) */

Definition at line 68 of file mii.h.

◆ MII_COMMAND_ACK

#define MII_COMMAND_ACK   0x02

Definition at line 48 of file mii.h.

◆ MII_COMMAND_READ

#define MII_COMMAND_READ   0x02

Definition at line 46 of file mii.h.

◆ MII_COMMAND_START

#define MII_COMMAND_START   0x01

Definition at line 45 of file mii.h.

◆ MII_COMMAND_WRITE

#define MII_COMMAND_WRITE   0x01

Definition at line 47 of file mii.h.

◆ MII_EXTSR

#define MII_EXTSR   0x0f /* Extended status register */

Definition at line 228 of file mii.h.

◆ MII_MMDAADR

#define MII_MMDAADR   0x0e /* MMD access address data register */

Definition at line 226 of file mii.h.

◆ MII_MMDACR

#define MII_MMDACR   0x0d /* MMD access control register */

Definition at line 218 of file mii.h.

◆ MII_NPHY

#define MII_NPHY   32 /* max # of PHYs per MII */

Definition at line 37 of file mii.h.

◆ MII_PHYIDR1

#define MII_PHYIDR1   0x02 /* ID register 1 (ro) */

Definition at line 100 of file mii.h.

◆ MII_PHYIDR2

#define MII_PHYIDR2   0x03 /* ID register 2 (ro) */

Definition at line 102 of file mii.h.

◆ MII_PSECR

#define MII_PSECR   0x0b /* PSE control register */

Definition at line 193 of file mii.h.

◆ MII_PSESR

#define MII_PSESR   0x0c /* PSE status register */

Definition at line 202 of file mii.h.

◆ MMDACR_DADDRMASK

#define MMDACR_DADDRMASK   0x001f /* device address */

Definition at line 220 of file mii.h.

◆ MMDACR_FN_ADDRESS

#define MMDACR_FN_ADDRESS   (0 << 14) /* address */

Definition at line 221 of file mii.h.

◆ MMDACR_FN_DATANPI

#define MMDACR_FN_DATANPI   (1 << 14) /* data, no post increment */

Definition at line 222 of file mii.h.

◆ MMDACR_FN_DATAPIRW

#define MMDACR_FN_DATAPIRW   (2 << 14) /* data, post increment on r/w */

Definition at line 223 of file mii.h.

◆ MMDACR_FN_DATAPIW

#define MMDACR_FN_DATAPIW   (3 << 14) /* data, post increment on wr only */

Definition at line 224 of file mii.h.

◆ MMDACR_FUNCMASK

#define MMDACR_FUNCMASK   0xc000 /* function */

Definition at line 219 of file mii.h.

◆ PSECR_FOPOWTST

#define PSECR_FOPOWTST   0x0002 /* Force Power Test Mode */

Definition at line 198 of file mii.h.

◆ PSECR_PACTLMASK

#define PSECR_PACTLMASK   0x000c /* pair control mask */

Definition at line 194 of file mii.h.

◆ PSECR_PINOUTA

#define PSECR_PINOUTA   0x0004 /* PSE pinout Alternative A */

Definition at line 197 of file mii.h.

◆ PSECR_PINOUTB

#define PSECR_PINOUTB   0x0008 /* PSE pinout Alternative B */

Definition at line 196 of file mii.h.

◆ PSECR_PSEDIS

#define PSECR_PSEDIS   0x0000 /* PSE Disabled */

Definition at line 200 of file mii.h.

◆ PSECR_PSEEN

#define PSECR_PSEEN   0x0001 /* PSE Enabled */

Definition at line 199 of file mii.h.

◆ PSECR_PSEENMASK

#define PSECR_PSEENMASK   0x0003 /* PSE enable mask */

Definition at line 195 of file mii.h.

◆ PSESR_INVALSIG

#define PSESR_INVALSIG   0x0400 /* Invalid PD signature detected */

Definition at line 205 of file mii.h.

◆ PSESR_MPSABSENT

#define PSESR_MPSABSENT   0x0080 /* MPS absent condition detected */

Definition at line 208 of file mii.h.

◆ PSESR_OVERLOAD

#define PSESR_OVERLOAD   0x0100 /* Overload condition detected */

Definition at line 207 of file mii.h.

◆ PSESR_PAIRCTABL

#define PSESR_PAIRCTABL   0x0001 /* PAIR Control Ability */

Definition at line 211 of file mii.h.

◆ PSESR_PDCL_0

#define PSESR_PDCL_0   (0 << 4) /* Class 0 */

Definition at line 216 of file mii.h.

◆ PSESR_PDCL_1

#define PSESR_PDCL_1   (1 << 4) /* Class 1 */

Definition at line 215 of file mii.h.

◆ PSESR_PDCL_2

#define PSESR_PDCL_2   (2 << 4) /* Class 2 */

Definition at line 214 of file mii.h.

◆ PSESR_PDCL_3

#define PSESR_PDCL_3   (3 << 4) /* Class 3 */

Definition at line 213 of file mii.h.

◆ PSESR_PDCL_4

#define PSESR_PDCL_4   (4 << 4) /* Class 4 */

Definition at line 212 of file mii.h.

◆ PSESR_PDCLMASK

#define PSESR_PDCLMASK   0x0070 /* PD Class mask */

Definition at line 209 of file mii.h.

◆ PSESR_PWRDENIED

#define PSESR_PWRDENIED   0x1000 /* Power Denied */

Definition at line 203 of file mii.h.

◆ PSESR_SHORTCIRC

#define PSESR_SHORTCIRC   0x0200 /* Short circuit condition detected */

Definition at line 206 of file mii.h.

◆ PSESR_STATMASK

#define PSESR_STATMASK   0x000e /* PSE Status mask */

Definition at line 210 of file mii.h.

◆ PSESR_VALSIG

#define PSESR_VALSIG   0x0800 /* Valid PD signature detected */

Definition at line 204 of file mii.h.


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