maltareg.h Source File

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maltareg.h
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1 /* $NetBSD: maltareg.h,v 1.1 2002/03/07 14:44:04 simonb Exp $ */
2 
3 #ifndef MALTAREG_H
4 #define MALTAREG_H
5 
6 /*
7  * Copyright 2002 Wasabi Systems, Inc.
8  * All rights reserved.
9  *
10  * Written by Simon Burge for Wasabi Systems, Inc.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  * notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  * notice, this list of conditions and the following disclaimer in the
19  * documentation and/or other materials provided with the distribution.
20  * 3. All advertising materials mentioning features or use of this software
21  * must display the following acknowledgement:
22  * This product includes software developed for the NetBSD Project by
23  * Wasabi Systems, Inc.
24  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
25  * or promote products derived from this software without specific prior
26  * written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
32  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38  * POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 /*
42  Memory Map
43 
44  0000.0000 * 128MB Typically SDRAM (on Core Board)
45  0800.0000 * 256MB Typically PCI
46  1800.0000 * 62MB Typically PCI
47  1be0.0000 * 2MB Typically System controller's internal registers
48  1c00.0000 * 32MB Typically not used
49  1e00.0000 4MB Monitor Flash
50  1e40.0000 12MB reserved
51  1f00.0000 12MB Switches
52  LEDs
53  ASCII display
54  Soft reset
55  FPGA revision number
56  CBUS UART (tty2)
57  General Purpose I/O
58  I2C controller
59  1f10.0000 * 11MB Typically System Controller specific
60  1fc0.0000 4MB Maps to Monitor Flash
61  1fd0.0000 * 3MB Typically System Controller specific
62 
63  * depends on implementation of the Core Board and of software
64  */
65 
66 /*
67  CPU interrupts
68 
69  NMI South Bridge or NMI button
70  0 South Bridge INTR
71  1 South Bridge SMI
72  2 CBUS UART (tty2)
73  3 COREHI (Core Card)
74  4 CORELO (Core Card)
75  5 Not used, driven inactive (typically CPU internal timer interrupt
76 
77  IRQ mapping (as used by YAMON)
78 
79  0 Timer South Bridge
80  1 Keyboard SuperIO
81  2 Reserved by South Bridge (for cascading)
82  3 UART (tty1) SuperIO
83  4 UART (tty0) SuperIO
84  5 Not used
85  6 Floppy Disk SuperIO
86  7 Parallel Port SuperIO
87  8 Real Time Clock South Bridge
88  9 I2C bus South Bridge
89  10 PCI A,B,eth PCI slot 1..4, Ethernet
90  11 PCI C,audio PCI slot 1..4, Audio, USB (South Bridge)
91  PCI D,USB
92  12 Mouse SuperIO
93  13 Reserved by South Bridge
94  14 Primary IDE Primary IDE slot
95  15 Secondary IDE Secondary IDE slot/Compact flash connector
96  */
97 
98 #define MALTA_SYSTEMRAM_BASE 0x00000000 /* System RAM: */
99 #define MALTA_SYSTEMRAM_SIZE 0x08000000 /* 128 MByte */
100 
101 #define MALTA_PCIMEM1_BASE 0x08000000 /* PCI 1 memory: */
102 #define MALTA_PCIMEM1_SIZE 0x08000000 /* 128 MByte */
103 
104 #define MALTA_PCIMEM2_BASE 0x10000000 /* PCI 2 memory: */
105 #define MALTA_PCIMEM2_SIZE 0x08000000 /* 128 MByte */
106 
107 #define MALTA_PCIMEM3_BASE 0x18000000 /* PCI 3 memory */
108 #define MALTA_PCIMEM3_SIZE 0x03e00000 /* 62 MByte */
109 
110 #define MALTA_CORECTRL_BASE 0x1be00000 /* Core control: */
111 #define MALTA_CORECTRL_SIZE 0x00200000 /* 2 MByte */
112 
113 #define MALTA_RESERVED_BASE1 0x1c000000 /* Reserved: */
114 #define MALTA_RESERVED_SIZE1 0x02000000 /* 32 MByte */
115 
116 #define MALTA_MONITORFLASH_BASE 0x1e000000 /* Monitor Flash: */
117 #define MALTA_MONITORFLASH_SIZE 0x003e0000 /* 4 MByte */
118 #define MALTA_MONITORFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */
119 
120 #define MALTA_FILEFLASH_BASE 0x1e3e0000 /* File Flash (for monitor): */
121 #define MALTA_FILEFLASH_SIZE 0x00020000 /* 128 KByte */
122 
123 #define MALTA_FILEFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */
124 
125 #define MALTA_RESERVED_BASE2 0x1e400000 /* Reserved: */
126 #define MALTA_RESERVED_SIZE2 0x00c00000 /* 12 MByte */
127 
128 #define MALTA_FPGA_BASE 0x1f000000 /* FPGA: */
129 #define MALTA_FPGA_SIZE 0x00c00000 /* 12 MByte */
130 
131 #define MALTA_NMISTATUS (MALTA_FPGA_BASE + 0x24)
132 #define MALTA_NMI_SB 0x2 /* Pending NMI from the South Bridge */
133 #define MALTA_NMI_ONNMI 0x1 /* Pending NMI from the ON/NMI push button */
134 
135 #define MALTA_NMIACK (MALTA_FPGA_BASE + 0x104)
136 #define MALTA_NMIACK_ONNMI 0x1 /* Write 1 to acknowledge ON/NMI */
137 
138 #define MALTA_SWITCH (MALTA_FPGA_BASE + 0x200)
139 #define MALTA_SWITCH_MASK 0xff /* settings of DIP switch S2 */
140 
141 #define MALTA_STATUS (MALTA_FPGA_BASE + 0x208)
142 #define MALTA_ST_MFWR 0x10 /* Monitor Flash is write protected (JP1) */
143 #define MALTA_S54 0x08 /* switch S5-4 - set YAMON factory default mode */
144 #define MALTA_S53 0x04 /* switch S5-3 */
145 #define MALTA_BIGEND 0x02 /* switch S5-2 - big endian mode */
146 
147 #define MALTA_JMPRS (MALTA_FPGA_BASE + 0x210)
148 #define MALTA_JMPRS_PCICLK 0x1c /* PCI clock frequency */
149 #define MALTA_JMPRS_EELOCK 0x02 /* I2C EEPROM is write protected */
150 
151 #define MALTA_LEDBAR (MALTA_FPGA_BASE + 0x408)
152 #define MALTA_ASCIIWORD (MALTA_FPGA_BASE + 0x410)
153 #define MALTA_ASCII_BASE (MALTA_FPGA_BASE + 0x418)
154 #define MALTA_ASCIIPOS0 0x00
155 #define MALTA_ASCIIPOS1 0x08
156 #define MALTA_ASCIIPOS2 0x10
157 #define MALTA_ASCIIPOS3 0x18
158 #define MALTA_ASCIIPOS4 0x20
159 #define MALTA_ASCIIPOS5 0x28
160 #define MALTA_ASCIIPOS6 0x30
161 #define MALTA_ASCIIPOS7 0x38
162 
163 #define MALTA_SOFTRES (MALTA_FPGA_BASE + 0x500)
164 #define MALTA_GORESET 0x42 /* write this to MALTA_SOFTRES for board reset */
165 
166 /*
167  * BRKRES is the number of milliseconds before a "break" on tty will
168  * trigger a reset. A value of 0 will disable the reset.
169  */
170 #define MALTA_BRKRES (MALTA_FPGA_BASE + 0x508)
171 #define MALTA_BRKRES_MASK 0xff
172 
173 #define MALTA_CBUSUART (MALTA_FPGA_BASE + 0x900)
174 /* 16C550C UART, 8 bit registers on 8 byte boundaries */
175 /* RXTX 0x00 */
176 /* INTEN 0x08 */
177 /* IIFIFO 0x10 */
178 /* LCTRL 0x18 */
179 /* MCTRL 0x20 */
180 /* LSTAT 0x28 */
181 /* MSTAT 0x30 */
182 /* SCRATCH 0x38 */
183 #define MALTA_CBUSUART_INTR 2
184 
185 #define MALTA_GPIO_BASE (MALTA_FPGA_BASE + 0xa00)
186 #define MALTA_GPOUT 0x0
187 #define MALTA_GPINP 0x8
188 
189 #define MALTA_I2C_BASE (MALTA_FPGA_BASE + 0xb00)
190 #define MALTA_I2CINP 0x00
191 #define MALTA_I2COE 0x08
192 #define MALTA_I2COUT 0x10
193 #define MALTA_I2CSEL 0x18
194 
195 #define MALTA_BOOTROM_BASE 0x1fc00000 /* Boot ROM: */
196 #define MALTA_BOOTROM_SIZE 0x00400000 /* 4 MByte */
197 
198 #define MALTA_REVISION 0x1fc00010
199 #define MALTA_REV_FPGRV 0xff0000 /* CBUS FPGA revision */
200 #define MALTA_REV_CORID 0x00fc00 /* Core Board ID */
201 #define MALTA_REV_CORRV 0x000300 /* Core Board Revision */
202 #define MALTA_REV_PROID 0x0000f0 /* Product ID */
203 #define MALTA_REV_PRORV 0x00000f /* Product Revision */
204 
205 /* PCI definitions */
206 #define MALTA_SOUTHBRIDGE_INTR 0
207 
208 #define MALTA_PCI0_IO_BASE MALTA_PCIMEM3_BASE
209 #define MALTA_PCI0_ADDR( addr ) (MALTA_PCI0_IO_BASE + (addr))
210 
211 #define MALTA_RTCADR 0x70 // MALTA_PCI_IO_ADDR8(0x70)
212 #define MALTA_RTCDAT 0x71 // MALTA_PCI_IO_ADDR8(0x71)
213 
214 #define MALTA_SMSC_COM1_ADR 0x3f8
215 #define MALTA_SMSC_COM2_ADR 0x2f8
216 #define MALTA_UART0ADR MALTA_SMSC_COM1_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_COM1_ADR)
217 #define MALTA_UART1ADR MALTA_SMSC_COM2_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_COM2_ADR)
218 
219 #define MALTA_SMSC_1284_ADR 0x378
220 #define MALTA_1284ADR MALTA_SMSC_1284_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_1284_ADR)
221 
222 #define MALTA_SMSC_FDD_ADR 0x3f0
223 #define MALTA_FDDADR MALTA_SMSC_FDD_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_FDD_ADR)
224 
225 #define MALTA_SMSC_KYBD_ADR 0x60 /* Fixed 0x60, 0x64 */
226 #define MALTA_KYBDADR MALTA_SMSC_KYBD_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_KYBD_ADR)
227 #define MALTA_SMSC_MOUSE_ADR MALTA_SMSC_KYBD_ADR
228 #define MALTA_MOUSEADR MALTA_KYBDADR
229 
230 
231 #define MALTA_DMA_PCI_PCIBASE 0x00000000UL
232 #define MALTA_DMA_PCI_PHYSBASE 0x00000000UL
233 #define MALTA_DMA_PCI_SIZE (256 * 1024 * 1024)
234 
235 #define MALTA_DMA_ISA_PCIBASE 0x00800000UL
236 #define MALTA_DMA_ISA_PHYSBASE 0x00000000UL
237 #define MALTA_DMA_ISA_SIZE (8 * 1024 * 1024)
238 
239 #ifndef _LOCORE
240 void led_bar(uint8_t);
241 void led_display_word(uint32_t);
242 void led_display_str(const char *);
243 void led_display_char(int, uint8_t);
244 #endif
245 
246 #endif /* MALTAREG_H */
void led_display_str(const char *)
void led_display_word(uint32_t)
void led_bar(uint8_t)
void led_display_char(int, uint8_t)

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