imcreg.h File Reference

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imcreg.h File Reference

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Macros

#define IMC_CPUCTRL0   0x1fa00004 /* CPU control, register 0 */
 
#define IMC_CPUCTRL0_REFMASK   0x0000000f /* # lines to refresh */
 
#define IMC_CPUCTRL0_RFE   0x00000010 /* refresh enable */
 
#define IMC_CPUCTRL0_GPR   0x00000020 /* GIO parity enable */
 
#define IMC_CPUCTRL0_MPR   0x00000040 /* memory parity enable */
 
#define IMC_CPUCTRL0_CPR   0x00000080 /* cpu bus parity enable */
 
#define IMC_CPUCTRL0_WDOG   0x00000100 /* watchdog enable */
 
#define IMC_CPUCTRL0_SIN   0x00000200 /* reset system */
 
#define IMC_CPUCTRL0_GRR   0x00000400 /* graphics reset */
 
#define IMC_CPUCTRL0_ENLOCK   0x00000800 /* enable EISA memory lock */
 
#define IMC_CPUCTRL0_CMDPAR   0x00001000 /* SysCmd parity enable */
 
#define IMC_CPUCTRL0_INTENA   0x00002000 /* enable CPU interrupts */
 
#define IMC_CPUCTRL0_SNOOPENA   0x00004000 /* enable gfx DMA snoop */
 
#define IMC_CPUCTRL0_PROM_WRENA
 
#define IMC_CPUCTRL0_WRST   0x00010000 /* warm restart (reset cpu) */
 
#define IMC_CPUCTRL0_LITTLE   0x00040000 /* MC little-endian toggle */
 
#define IMC_CPUCTRL0_WRRST   0x00080000 /* cpu warm reset */
 
#define IMC_CPUCTRL0_MUXHWMSK   0x01f00000 /* MUX fifo high-water mask */
 
#define IMC_CPUCTRL0_BADPAR
 
#define IMC_CPUCTRL0_NCHKMEMPAR
 
#define IMC_CPUCTRL0_BACK2   0x08000000 /* enable back2back GIO wrt */
 
#define IMC_CPUCTRL0_BUSRTMSK   0xf0000000 /* stall cycle for berr data */
 
#define IMC_CPUCTRL1   0x1fa0000c /* CPU control, register 1 */
 
#define IMC_CPUCTRL1_MCHWMSK   0x0000000f /* MC FIFO high water mask */
 
#define IMC_CPUCTRL1_ABORTEN   0x00000010 /* Enable GIO bus timeouts */
 
#define IMC_CPUCTRL1_HPCFX   0x00001000 /* HPC endian fix */
 
#define IMC_CPUCTRL1_HPCLITTLE   0x00002000 /* HPC DMA is little-endian */
 
#define IMC_CPUCTRL1_EXP0FX   0x00004000 /* EXP0 endian fix */
 
#define IMC_CPUCTRL1_EXP0LITTLE   0x00008000 /* EXP0 DMA is little-endian */
 
#define IMC_CPUCTRL1_EXP1FX   0x00010000 /* EXP1 endian fix */
 
#define IMC_CPUCTRL1_EXP1LITTLE   0x00020000 /* EXP1 DMA is little-endian */
 
#define IMC_WDOG   0x1fa00014 /* Watchdog counter */
 
#define IMC_WDOG_MASK   0x001fffff /* counter mask */
 
#define IMC_SYSID   0x1fa0001c /* MC revision register */
 
#define IMC_SYSID_REVMASK   0x0000000f /* MC revision mask */
 
#define IMC_SYSID_HAVEISA   0x00000010 /* EISA present */
 
#define IMC_RPSSDIV   0x1fa0002c /* RPSS divider */
 
#define IMC_RPSSDIV_DIVMSK   0x000000ff /* RPC divider mask */
 
#define IMC_RPSSDIV_INCMSK   0x0000ff00 /* RPC increment mask */
 
#define IMC_EEPROM   0x1fa00034 /* EEPROM serial interface */
 
#define IMC_EEPROM_CS   0x00000002 /* EEPROM chip select */
 
#define IMC_EEPROM_SCK   0x00000004 /* EEPROM serial clock */
 
#define IMC_EEPROM_SO   0x00000008 /* Serial data to EEPROM */
 
#define IMC_EEPROM_SI   0x00000010 /* Serial data from EEPROM */
 
#define IMC_CTRLD   0x1fa00044 /* Refresh counter preload */
 
#define IMC_CTRLD_MSK   0x000000ff /* Counter preload mask */
 
#define IMC_REFCTR   0x1fa0004c /* Refresh counter */
 
#define IMC_REFCTR_MSK   0x000000ff /* Refresh counter mask */
 
#define IMC_GIO64ARB   0x1fa00084 /* GIO64 arbitration params */
 
#define IMC_GIO64ARB_HPC64   0x00000001 /* HPC addr size (32/64bit) */
 
#define IMC_GIO64ARB_GRX64   0x00000002 /* Gfx addr size (32/64bit) */
 
#define IMC_GIO64ARB_EXP064   0x00000004 /* EXP0 addr size (32/64bit) */
 
#define IMC_GIO64ARB_EXP164   0x00000008 /* EXP0 addr size (32/64bit) */
 
#define IMC_GIO64ARB_EISA64   0x00000010 /* EISA addr size (32/64bit) */
 
#define IMC_GIO64ARB_HPCEXP64   0x00000020 /* HPC2 addr size (32/64bit) */
 
#define IMC_GIO64ARB_GRXRT   0x00000040 /* Gfx is realtime device */
 
#define IMC_GIO64ARB_EXP0RT   0x00000080 /* EXP0 is realtime device */
 
#define IMC_GIO64ARB_EXP1RT   0x00000100 /* EXP1 is realtime device */
 
#define IMC_GIO64ARB_EISAMST   0x00000200 /* EISA can be busmaster */
 
#define IMC_GIO64ARB_ONEGIO   0x00000400 /* One one GIO64 bus */
 
#define IMC_GIO64ARB_GRXMST   0x00000800 /* Gfx can be busmaster */
 
#define IMC_GIO64ARB_EXP0MST   0x00001000 /* EXP0 can be busmaster */
 
#define IMC_GIO64ARB_EXP1MST   0x00002000 /* EXP1 can be busmaster */
 
#define IMC_GIO64ARB_EXP0PIPE   0x00004000 /* EXP0 is pipelined */
 
#define IMC_GIO64ARB_EXP1PIPE   0x00008000 /* EXP1 is pipelined */
 
#define IMC_CPUTIME   0x1fa0008c /* Arbiter CPU time period */
 
#define IMC_LBTIME   0x1fa0009c /* Arbiter long-burst time */
 
#define IMC_MEMCFG0   0x1fa000c4 /* Mem config, regsiter 0 */
 
#define IMC_MEMCFG1   0x1fa000cc /* Mem config, regsiter 1 */
 
#define IMC_CPU_MEMACC   0x1fa000d4 /* CPU mem access config */
 
#define IMC_GIO_MEMACC   0x1fa000dc /* GIO mem access config */
 
#define IMC_CPU_ERRADDR   0x1fa000e4 /* CPU error address */
 
#define IMC_CPU_ERRSTAT   0x1fa000ec /* CPU error status */
 
#define IMC_GIO_ERRADDR   0x1fa000f4 /* GIO error address */
 
#define IMC_GIO_ERRSTAT   0x1fa000fc /* GIO error status */
 

Macro Definition Documentation

◆ IMC_CPU_ERRADDR

#define IMC_CPU_ERRADDR   0x1fa000e4 /* CPU error address */

Definition at line 127 of file imcreg.h.

◆ IMC_CPU_ERRSTAT

#define IMC_CPU_ERRSTAT   0x1fa000ec /* CPU error status */

Definition at line 129 of file imcreg.h.

◆ IMC_CPU_MEMACC

#define IMC_CPU_MEMACC   0x1fa000d4 /* CPU mem access config */

Definition at line 123 of file imcreg.h.

◆ IMC_CPUCTRL0

#define IMC_CPUCTRL0   0x1fa00004 /* CPU control, register 0 */

Definition at line 34 of file imcreg.h.

Referenced by DEVICE_ACCESS().

◆ IMC_CPUCTRL0_BACK2

#define IMC_CPUCTRL0_BACK2   0x08000000 /* enable back2back GIO wrt */

Definition at line 59 of file imcreg.h.

◆ IMC_CPUCTRL0_BADPAR

#define IMC_CPUCTRL0_BADPAR
Value:
0x02000000 /* generate bad parity on
* CPU->memory writes */

Definition at line 55 of file imcreg.h.

◆ IMC_CPUCTRL0_BUSRTMSK

#define IMC_CPUCTRL0_BUSRTMSK   0xf0000000 /* stall cycle for berr data */

Definition at line 60 of file imcreg.h.

◆ IMC_CPUCTRL0_CMDPAR

#define IMC_CPUCTRL0_CMDPAR   0x00001000 /* SysCmd parity enable */

Definition at line 45 of file imcreg.h.

◆ IMC_CPUCTRL0_CPR

#define IMC_CPUCTRL0_CPR   0x00000080 /* cpu bus parity enable */

Definition at line 40 of file imcreg.h.

◆ IMC_CPUCTRL0_ENLOCK

#define IMC_CPUCTRL0_ENLOCK   0x00000800 /* enable EISA memory lock */

Definition at line 44 of file imcreg.h.

◆ IMC_CPUCTRL0_GPR

#define IMC_CPUCTRL0_GPR   0x00000020 /* GIO parity enable */

Definition at line 38 of file imcreg.h.

◆ IMC_CPUCTRL0_GRR

#define IMC_CPUCTRL0_GRR   0x00000400 /* graphics reset */

Definition at line 43 of file imcreg.h.

◆ IMC_CPUCTRL0_INTENA

#define IMC_CPUCTRL0_INTENA   0x00002000 /* enable CPU interrupts */

Definition at line 46 of file imcreg.h.

◆ IMC_CPUCTRL0_LITTLE

#define IMC_CPUCTRL0_LITTLE   0x00040000 /* MC little-endian toggle */

Definition at line 52 of file imcreg.h.

◆ IMC_CPUCTRL0_MPR

#define IMC_CPUCTRL0_MPR   0x00000040 /* memory parity enable */

Definition at line 39 of file imcreg.h.

◆ IMC_CPUCTRL0_MUXHWMSK

#define IMC_CPUCTRL0_MUXHWMSK   0x01f00000 /* MUX fifo high-water mask */

Definition at line 54 of file imcreg.h.

◆ IMC_CPUCTRL0_NCHKMEMPAR

#define IMC_CPUCTRL0_NCHKMEMPAR
Value:
0x04000000 /* disable CPU parity check
* on memory reads. */

Definition at line 57 of file imcreg.h.

◆ IMC_CPUCTRL0_PROM_WRENA

#define IMC_CPUCTRL0_PROM_WRENA
Value:
0x00008000 /* disable buserr on PROM
* writes */

Definition at line 48 of file imcreg.h.

◆ IMC_CPUCTRL0_REFMASK

#define IMC_CPUCTRL0_REFMASK   0x0000000f /* # lines to refresh */

Definition at line 36 of file imcreg.h.

◆ IMC_CPUCTRL0_RFE

#define IMC_CPUCTRL0_RFE   0x00000010 /* refresh enable */

Definition at line 37 of file imcreg.h.

◆ IMC_CPUCTRL0_SIN

#define IMC_CPUCTRL0_SIN   0x00000200 /* reset system */

Definition at line 42 of file imcreg.h.

◆ IMC_CPUCTRL0_SNOOPENA

#define IMC_CPUCTRL0_SNOOPENA   0x00004000 /* enable gfx DMA snoop */

Definition at line 47 of file imcreg.h.

◆ IMC_CPUCTRL0_WDOG

#define IMC_CPUCTRL0_WDOG   0x00000100 /* watchdog enable */

Definition at line 41 of file imcreg.h.

◆ IMC_CPUCTRL0_WRRST

#define IMC_CPUCTRL0_WRRST   0x00080000 /* cpu warm reset */

Definition at line 53 of file imcreg.h.

◆ IMC_CPUCTRL0_WRST

#define IMC_CPUCTRL0_WRST   0x00010000 /* warm restart (reset cpu) */

Definition at line 50 of file imcreg.h.

◆ IMC_CPUCTRL1

#define IMC_CPUCTRL1   0x1fa0000c /* CPU control, register 1 */

Definition at line 62 of file imcreg.h.

◆ IMC_CPUCTRL1_ABORTEN

#define IMC_CPUCTRL1_ABORTEN   0x00000010 /* Enable GIO bus timeouts */

Definition at line 64 of file imcreg.h.

◆ IMC_CPUCTRL1_EXP0FX

#define IMC_CPUCTRL1_EXP0FX   0x00004000 /* EXP0 endian fix */

Definition at line 68 of file imcreg.h.

◆ IMC_CPUCTRL1_EXP0LITTLE

#define IMC_CPUCTRL1_EXP0LITTLE   0x00008000 /* EXP0 DMA is little-endian */

Definition at line 69 of file imcreg.h.

◆ IMC_CPUCTRL1_EXP1FX

#define IMC_CPUCTRL1_EXP1FX   0x00010000 /* EXP1 endian fix */

Definition at line 70 of file imcreg.h.

◆ IMC_CPUCTRL1_EXP1LITTLE

#define IMC_CPUCTRL1_EXP1LITTLE   0x00020000 /* EXP1 DMA is little-endian */

Definition at line 71 of file imcreg.h.

◆ IMC_CPUCTRL1_HPCFX

#define IMC_CPUCTRL1_HPCFX   0x00001000 /* HPC endian fix */

Definition at line 66 of file imcreg.h.

◆ IMC_CPUCTRL1_HPCLITTLE

#define IMC_CPUCTRL1_HPCLITTLE   0x00002000 /* HPC DMA is little-endian */

Definition at line 67 of file imcreg.h.

◆ IMC_CPUCTRL1_MCHWMSK

#define IMC_CPUCTRL1_MCHWMSK   0x0000000f /* MC FIFO high water mask */

Definition at line 63 of file imcreg.h.

◆ IMC_CPUTIME

#define IMC_CPUTIME   0x1fa0008c /* Arbiter CPU time period */

Definition at line 115 of file imcreg.h.

◆ IMC_CTRLD

#define IMC_CTRLD   0x1fa00044 /* Refresh counter preload */

Definition at line 91 of file imcreg.h.

◆ IMC_CTRLD_MSK

#define IMC_CTRLD_MSK   0x000000ff /* Counter preload mask */

Definition at line 92 of file imcreg.h.

◆ IMC_EEPROM

#define IMC_EEPROM   0x1fa00034 /* EEPROM serial interface */

Definition at line 84 of file imcreg.h.

Referenced by DEVICE_ACCESS().

◆ IMC_EEPROM_CS

#define IMC_EEPROM_CS   0x00000002 /* EEPROM chip select */

Definition at line 86 of file imcreg.h.

◆ IMC_EEPROM_SCK

#define IMC_EEPROM_SCK   0x00000004 /* EEPROM serial clock */

Definition at line 87 of file imcreg.h.

◆ IMC_EEPROM_SI

#define IMC_EEPROM_SI   0x00000010 /* Serial data from EEPROM */

Definition at line 89 of file imcreg.h.

◆ IMC_EEPROM_SO

#define IMC_EEPROM_SO   0x00000008 /* Serial data to EEPROM */

Definition at line 88 of file imcreg.h.

◆ IMC_GIO64ARB

#define IMC_GIO64ARB   0x1fa00084 /* GIO64 arbitration params */

Definition at line 97 of file imcreg.h.

◆ IMC_GIO64ARB_EISA64

#define IMC_GIO64ARB_EISA64   0x00000010 /* EISA addr size (32/64bit) */

Definition at line 102 of file imcreg.h.

◆ IMC_GIO64ARB_EISAMST

#define IMC_GIO64ARB_EISAMST   0x00000200 /* EISA can be busmaster */

Definition at line 107 of file imcreg.h.

◆ IMC_GIO64ARB_EXP064

#define IMC_GIO64ARB_EXP064   0x00000004 /* EXP0 addr size (32/64bit) */

Definition at line 100 of file imcreg.h.

◆ IMC_GIO64ARB_EXP0MST

#define IMC_GIO64ARB_EXP0MST   0x00001000 /* EXP0 can be busmaster */

Definition at line 110 of file imcreg.h.

◆ IMC_GIO64ARB_EXP0PIPE

#define IMC_GIO64ARB_EXP0PIPE   0x00004000 /* EXP0 is pipelined */

Definition at line 112 of file imcreg.h.

◆ IMC_GIO64ARB_EXP0RT

#define IMC_GIO64ARB_EXP0RT   0x00000080 /* EXP0 is realtime device */

Definition at line 105 of file imcreg.h.

◆ IMC_GIO64ARB_EXP164

#define IMC_GIO64ARB_EXP164   0x00000008 /* EXP0 addr size (32/64bit) */

Definition at line 101 of file imcreg.h.

◆ IMC_GIO64ARB_EXP1MST

#define IMC_GIO64ARB_EXP1MST   0x00002000 /* EXP1 can be busmaster */

Definition at line 111 of file imcreg.h.

◆ IMC_GIO64ARB_EXP1PIPE

#define IMC_GIO64ARB_EXP1PIPE   0x00008000 /* EXP1 is pipelined */

Definition at line 113 of file imcreg.h.

◆ IMC_GIO64ARB_EXP1RT

#define IMC_GIO64ARB_EXP1RT   0x00000100 /* EXP1 is realtime device */

Definition at line 106 of file imcreg.h.

◆ IMC_GIO64ARB_GRX64

#define IMC_GIO64ARB_GRX64   0x00000002 /* Gfx addr size (32/64bit) */

Definition at line 99 of file imcreg.h.

◆ IMC_GIO64ARB_GRXMST

#define IMC_GIO64ARB_GRXMST   0x00000800 /* Gfx can be busmaster */

Definition at line 109 of file imcreg.h.

◆ IMC_GIO64ARB_GRXRT

#define IMC_GIO64ARB_GRXRT   0x00000040 /* Gfx is realtime device */

Definition at line 104 of file imcreg.h.

◆ IMC_GIO64ARB_HPC64

#define IMC_GIO64ARB_HPC64   0x00000001 /* HPC addr size (32/64bit) */

Definition at line 98 of file imcreg.h.

◆ IMC_GIO64ARB_HPCEXP64

#define IMC_GIO64ARB_HPCEXP64   0x00000020 /* HPC2 addr size (32/64bit) */

Definition at line 103 of file imcreg.h.

◆ IMC_GIO64ARB_ONEGIO

#define IMC_GIO64ARB_ONEGIO   0x00000400 /* One one GIO64 bus */

Definition at line 108 of file imcreg.h.

◆ IMC_GIO_ERRADDR

#define IMC_GIO_ERRADDR   0x1fa000f4 /* GIO error address */

Definition at line 131 of file imcreg.h.

◆ IMC_GIO_ERRSTAT

#define IMC_GIO_ERRSTAT   0x1fa000fc /* GIO error status */

Definition at line 133 of file imcreg.h.

◆ IMC_GIO_MEMACC

#define IMC_GIO_MEMACC   0x1fa000dc /* GIO mem access config */

Definition at line 125 of file imcreg.h.

◆ IMC_LBTIME

#define IMC_LBTIME   0x1fa0009c /* Arbiter long-burst time */

Definition at line 117 of file imcreg.h.

◆ IMC_MEMCFG0

#define IMC_MEMCFG0   0x1fa000c4 /* Mem config, regsiter 0 */

Definition at line 119 of file imcreg.h.

Referenced by DEVICE_ACCESS().

◆ IMC_MEMCFG1

#define IMC_MEMCFG1   0x1fa000cc /* Mem config, regsiter 1 */

Definition at line 121 of file imcreg.h.

Referenced by DEVICE_ACCESS().

◆ IMC_REFCTR

#define IMC_REFCTR   0x1fa0004c /* Refresh counter */

Definition at line 94 of file imcreg.h.

◆ IMC_REFCTR_MSK

#define IMC_REFCTR_MSK   0x000000ff /* Refresh counter mask */

Definition at line 95 of file imcreg.h.

◆ IMC_RPSSDIV

#define IMC_RPSSDIV   0x1fa0002c /* RPSS divider */

Definition at line 80 of file imcreg.h.

◆ IMC_RPSSDIV_DIVMSK

#define IMC_RPSSDIV_DIVMSK   0x000000ff /* RPC divider mask */

Definition at line 81 of file imcreg.h.

◆ IMC_RPSSDIV_INCMSK

#define IMC_RPSSDIV_INCMSK   0x0000ff00 /* RPC increment mask */

Definition at line 82 of file imcreg.h.

◆ IMC_SYSID

#define IMC_SYSID   0x1fa0001c /* MC revision register */

Definition at line 76 of file imcreg.h.

Referenced by DEVICE_ACCESS().

◆ IMC_SYSID_HAVEISA

#define IMC_SYSID_HAVEISA   0x00000010 /* EISA present */

Definition at line 78 of file imcreg.h.

◆ IMC_SYSID_REVMASK

#define IMC_SYSID_REVMASK   0x0000000f /* MC revision mask */

Definition at line 77 of file imcreg.h.

◆ IMC_WDOG

#define IMC_WDOG   0x1fa00014 /* Watchdog counter */

Definition at line 73 of file imcreg.h.

Referenced by DEVICE_ACCESS().

◆ IMC_WDOG_MASK

#define IMC_WDOG_MASK   0x001fffff /* counter mask */

Definition at line 74 of file imcreg.h.


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