dev_eagle.cc Source File

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dev_eagle.cc
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1 /*
2  * Copyright (C) 2003-2009 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * COMMENT: Motorola MPC105 "Eagle" host bridge
29  */
30 
31 #include <stdio.h>
32 #include <stdlib.h>
33 #include <string.h>
34 
35 #include "bus_isa.h"
36 #include "bus_pci.h"
37 #include "cpu.h"
38 #include "device.h"
39 #include "interrupt.h"
40 #include "machine.h"
41 #include "memory.h"
42 #include "misc.h"
43 
44 
45 struct eagle_data {
46  struct interrupt irq;
47 
48  struct pci_data *pci_data;
49 };
50 
51 
53 {
54  struct eagle_data *d = (struct eagle_data *) extra;
55  uint64_t idata = 0, odata = 0;
56  int bus, dev, func, reg;
57 
58  if (writeflag == MEM_WRITE)
60 
61  /*
62  * Pass accesses to ISA ports 0xcf8 and 0xcfc onto bus_pci_*:
63  */
64 
65  switch (relative_addr) {
66 
67  case 0: /* Address: */
68  bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
69  bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
70  break;
71 
72  case 4: /* Data: */
73  bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
74  &odata : &idata, len, writeflag);
75  break;
76  }
77 
78  if (writeflag == MEM_READ)
80 
81  return 1;
82 }
83 
84 
85 DEVINIT(eagle)
86 {
87  struct eagle_data *d;
88  uint64_t pci_io_offset, pci_mem_offset;
89  uint64_t isa_portbase = 0, isa_membase = 0;
90  uint64_t pci_portbase = 0, pci_membase = 0;
91  char pci_irq_base[300];
92  char isa_irq_base[300];
93 
94  CHECK_ALLOCATION(d = (struct eagle_data *) malloc(sizeof(struct eagle_data)));
95  memset(d, 0, sizeof(struct eagle_data));
96 
97  /* The interrupt path to the CPU at which we are connected: */
99 
100  /*
101  * According to http://www.beatjapan.org/mirror/www.be.com/
102  * aboutbe/benewsletter/Issue27.html#Cookbook :
103  *
104  * "HARDWARE MEMORY MAP
105  * The MPC105 defines the physical memory map of the system as
106  * follows:
107  *
108  * Start Size Description
109  *
110  * 0x00000000 0x40000000 Physical RAM
111  * 0x40000000 0x40000000 Other system memory
112  * (motherboard glue regs)
113  * 0x80000000 0x00800000 ISA I/O
114  * 0x81000000 0x3E800000 PCI I/O
115  * 0xBFFFFFF0 0x00000010 PCI/ISA interrupt acknowledge
116  * 0xC0000000 0x3F000000 PCI memory
117  * 0xFF000000 0x01000000 ROM/flash
118  */
119 
120  /* TODO: Make these work like the BE web page stated... */
121  pci_io_offset = 0x80000000ULL;
122  pci_mem_offset = 0xc0000000ULL;
123  pci_portbase = 0x00000000ULL;
124  pci_membase = 0x00000000ULL;
125  isa_portbase = 0x80000000ULL;
126  isa_membase = 0xc0000000ULL;
127 
128  switch (devinit->machine->machine_type) {
129  /* case MACHINE_BEBOX:
130  snprintf(pci_irq_base, sizeof(pci_irq_base), "%s.bebox",
131  devinit->interrupt_path);
132  snprintf(isa_irq_base, sizeof(isa_irq_base), "%s.bebox.5",
133  devinit->interrupt_path);
134  break; */
135  default:
136  snprintf(pci_irq_base, sizeof(pci_irq_base), "%s",
138  snprintf(isa_irq_base, sizeof(isa_irq_base), "%s",
140  }
141 
142  /* Create a PCI bus: */
144  pci_io_offset, pci_mem_offset,
145  pci_portbase, pci_membase, pci_irq_base,
146  isa_portbase, isa_membase, isa_irq_base);
147 
148  /* Add the PCI glue for the controller itself: */
150  devinit->machine->memory, 0, 0, 0, "eagle");
151 
152  /* ADDR and DATA configuration ports in ISA space: */
154  isa_portbase + BUS_PCI_ADDR, 8, dev_eagle_access, d,
155  DM_DEFAULT, NULL);
156 
157  switch (devinit->machine->machine_type) {
158 
159  /* case MACHINE_BEBOX:
160  bus_isa_init(devinit->machine, isa_irq_base,
161  BUS_ISA_IDE0 | BUS_ISA_VGA, isa_portbase, isa_membase);
162  bus_pci_add(devinit->machine, d->pci_data,
163  devinit->machine->memory, 0, 11, 0, "i82378zb");
164  break; */
165 
166  case MACHINE_PREP:
168  devinit->machine->memory, 0, 11, 0, "ibm_isa");
169  break;
170 
171  case MACHINE_MVMEPPC:
172  bus_isa_init(devinit->machine, isa_irq_base,
173  BUS_ISA_LPTBASE_3BC, isa_portbase, isa_membase);
174 
175  switch (devinit->machine->machine_subtype) {
178  devinit->machine->memory, 0, 11, 0, "i82378zb");
179  break;
180  default:fatal("unimplemented machine subtype for "
181  "eagle/mvmeppc\n");
182  exit(1);
183  }
184  break;
185 
186  default:fatal("unimplemented machine type for eagle\n");
187  exit(1);
188  }
189 
191 
192  return 1;
193 }
194 
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
Definition: memory.cc:55
void fatal(const char *fmt,...)
Definition: main.cc:152
#define BUS_ISA_LPTBASE_3BC
Definition: bus_isa.h:66
#define DM_DEFAULT
Definition: memory.h:130
int machine_type
Definition: machine.h:111
#define MEM_READ
Definition: memory.h:116
struct memory * memory
Definition: machine.h:126
void bus_pci_add(struct machine *machine, struct pci_data *pci_data, struct memory *mem, int bus, int device, int function, const char *name)
Definition: bus_pci.cc:216
#define reg(x)
void * return_ptr
Definition: device.h:56
#define MACHINE_MVMEPPC_1600
Definition: machine.h:323
#define MACHINE_MVMEPPC
Definition: machine.h:230
#define CHECK_ALLOCATION(ptr)
Definition: misc.h:239
void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data, int bus, int device, int function, int reg)
Definition: bus_pci.cc:196
u_short data
Definition: siireg.h:79
#define MACHINE_PREP
Definition: machine.h:228
#define MEM_WRITE
Definition: memory.h:117
DEVICE_ACCESS(eagle)
Definition: dev_eagle.cc:52
DEVINIT(eagle)
Definition: dev_eagle.cc:85
Definition: device.h:40
#define INTERRUPT_CONNECT(name, istruct)
Definition: interrupt.h:77
Definition: cpu.h:326
struct machine * machine
Definition: device.h:41
struct bus_isa_data * bus_isa_init(struct machine *machine, char *interrupt_base_path, uint32_t bus_isa_flags, uint64_t isa_portbase, uint64_t isa_membase)
Definition: bus_isa.cc:174
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
Definition: memory.cc:89
struct interrupt irq
Definition: dev_eagle.cc:46
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
Definition: memory.cc:339
#define BUS_PCI_ADDR
Definition: bus_pci.h:138
void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg)
Definition: bus_pci.cc:76
struct pci_data * bus_pci_init(struct machine *machine, const char *irq_path, uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset, uint64_t pci_portbase, uint64_t pci_membase, const char *pci_irqbase, uint64_t isa_portbase, uint64_t isa_membase, const char *isa_irqbase)
Definition: bus_pci.cc:355
int machine_subtype
Definition: machine.h:112
struct pci_data * pci_data
Definition: dev_eagle.cc:48
void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data, uint64_t *data, int len, int writeflag)
Definition: bus_pci.cc:95
#define MEM_PCI_LITTLE_ENDIAN
Definition: memory.h:97
char * interrupt_path
Definition: device.h:50

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