46 #define PCI_CBMEM 0x10 48 #define PCI_INTERFACE_OHCI 0x10 52 #define OHCI_REVISION 0x00 53 #define OHCI_REV_LO(rev) ((rev)&0xf) 54 #define OHCI_REV_HI(rev) (((rev)>>4)&0xf) 55 #define OHCI_REV_LEGACY(rev) ((rev) & 0x100) 57 #define OHCI_CONTROL 0x04 58 #define OHCI_CBSR_MASK 0x00000003 59 #define OHCI_RATIO_1_1 0x00000000 60 #define OHCI_RATIO_1_2 0x00000001 61 #define OHCI_RATIO_1_3 0x00000002 62 #define OHCI_RATIO_1_4 0x00000003 63 #define OHCI_PLE 0x00000004 64 #define OHCI_IE 0x00000008 65 #define OHCI_CLE 0x00000010 66 #define OHCI_BLE 0x00000020 67 #define OHCI_HCFS_MASK 0x000000c0 68 #define OHCI_HCFS_RESET 0x00000000 69 #define OHCI_HCFS_RESUME 0x00000040 70 #define OHCI_HCFS_OPERATIONAL 0x00000080 71 #define OHCI_HCFS_SUSPEND 0x000000c0 72 #define OHCI_IR 0x00000100 73 #define OHCI_RWC 0x00000200 74 #define OHCI_RWE 0x00000400 75 #define OHCI_COMMAND_STATUS 0x08 76 #define OHCI_HCR 0x00000001 77 #define OHCI_CLF 0x00000002 78 #define OHCI_BLF 0x00000004 79 #define OHCI_OCR 0x00000008 80 #define OHCI_SOC_MASK 0x00030000 81 #define OHCI_INTERRUPT_STATUS 0x0c 82 #define OHCI_SO 0x00000001 83 #define OHCI_WDH 0x00000002 84 #define OHCI_SF 0x00000004 85 #define OHCI_RD 0x00000008 86 #define OHCI_UE 0x00000010 87 #define OHCI_FNO 0x00000020 88 #define OHCI_RHSC 0x00000040 89 #define OHCI_OC 0x40000000 90 #define OHCI_MIE 0x80000000 91 #define OHCI_INTERRUPT_ENABLE 0x10 92 #define OHCI_INTERRUPT_DISABLE 0x14 93 #define OHCI_HCCA 0x18 94 #define OHCI_PERIOD_CURRENT_ED 0x1c 95 #define OHCI_CONTROL_HEAD_ED 0x20 96 #define OHCI_CONTROL_CURRENT_ED 0x24 97 #define OHCI_BULK_HEAD_ED 0x28 98 #define OHCI_BULK_CURRENT_ED 0x2c 99 #define OHCI_DONE_HEAD 0x30 100 #define OHCI_FM_INTERVAL 0x34 101 #define OHCI_GET_IVAL(s) ((s) & 0x3fff) 102 #define OHCI_GET_FSMPS(s) (((s) >> 16) & 0x7fff) 103 #define OHCI_FIT 0x80000000 104 #define OHCI_FM_REMAINING 0x38 105 #define OHCI_FM_NUMBER 0x3c 106 #define OHCI_PERIODIC_START 0x40 107 #define OHCI_LS_THRESHOLD 0x44 108 #define OHCI_RH_DESCRIPTOR_A 0x48 109 #define OHCI_GET_NDP(s) ((s) & 0xff) 110 #define OHCI_PSM 0x0100 111 #define OHCI_NPS 0x0200 112 #define OHCI_DT 0x0400 113 #define OHCI_OCPM 0x0800 114 #define OHCI_NOCP 0x1000 115 #define OHCI_GET_POTPGT(s) ((s) >> 24) 116 #define OHCI_RH_DESCRIPTOR_B 0x4c 117 #define OHCI_RH_STATUS 0x50 118 #define OHCI_LPS 0x00000001 119 #define OHCI_OCI 0x00000002 120 #define OHCI_DRWE 0x00008000 121 #define OHCI_LPSC 0x00010000 122 #define OHCI_CCIC 0x00020000 123 #define OHCI_CRWE 0x80000000 124 #define OHCI_RH_PORT_STATUS(n) (0x50 + (n)*4) 126 #define OHCI_LES (OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE) 127 #define OHCI_ALL_INTRS (OHCI_SO | OHCI_WDH | OHCI_SF | OHCI_RD | OHCI_UE | \ 128 OHCI_FNO | OHCI_RHSC | OHCI_OC) 129 #define OHCI_NORMAL_INTRS (OHCI_SO | OHCI_WDH | OHCI_RD | OHCI_UE | OHCI_RHSC) 131 #define OHCI_FSMPS(i) (((i-210)*6/7) << 16) 132 #define OHCI_PERIODIC(i) ((i)*9/10) 136 #define OHCI_NO_INTRS 32 141 #define OHCI_DONE_INTRS 1 143 #define OHCI_HCCA_SIZE 256 144 #define OHCI_HCCA_ALIGN 256 146 #define OHCI_PAGE_SIZE 0x1000 147 #define OHCI_PAGE(x) ((x) &~ 0xfff) 148 #define OHCI_PAGE_OFFSET(x) ((x) & 0xfff) 152 #define OHCI_ED_GET_FA(s) ((s) & 0x7f) 153 #define OHCI_ED_ADDRMASK 0x0000007f 154 #define OHCI_ED_SET_FA(s) (s) 155 #define OHCI_ED_GET_EN(s) (((s) >> 7) & 0xf) 156 #define OHCI_ED_SET_EN(s) ((s) << 7) 157 #define OHCI_ED_DIR_MASK 0x00001800 158 #define OHCI_ED_DIR_TD 0x00000000 159 #define OHCI_ED_DIR_OUT 0x00000800 160 #define OHCI_ED_DIR_IN 0x00001000 161 #define OHCI_ED_SPEED 0x00002000 162 #define OHCI_ED_SKIP 0x00004000 163 #define OHCI_ED_FORMAT_GEN 0x00000000 164 #define OHCI_ED_FORMAT_ISO 0x00008000 165 #define OHCI_ED_GET_MAXP(s) (((s) >> 16) & 0x07ff) 166 #define OHCI_ED_SET_MAXP(s) ((s) << 16) 167 #define OHCI_ED_MAXPMASK (0x7ff << 16) 170 #define OHCI_HALTED 0x00000001 171 #define OHCI_TOGGLECARRY 0x00000002 172 #define OHCI_HEADMASK 0xfffffffc 176 #define OHCI_ED_ALIGN 16 180 #define OHCI_TD_R 0x00040000 181 #define OHCI_TD_DP_MASK 0x00180000 182 #define OHCI_TD_SETUP 0x00000000 183 #define OHCI_TD_OUT 0x00080000 184 #define OHCI_TD_IN 0x00100000 185 #define OHCI_TD_GET_DI(x) (((x) >> 21) & 7) 186 #define OHCI_TD_SET_DI(x) ((x) << 21) 187 #define OHCI_TD_NOINTR 0x00e00000 188 #define OHCI_TD_INTR_MASK 0x00e00000 189 #define OHCI_TD_TOGGLE_CARRY 0x00000000 190 #define OHCI_TD_TOGGLE_0 0x02000000 191 #define OHCI_TD_TOGGLE_1 0x03000000 192 #define OHCI_TD_TOGGLE_MASK 0x03000000 193 #define OHCI_TD_GET_EC(x) (((x) >> 26) & 3) 194 #define OHCI_TD_GET_CC(x) ((x) >> 28) 195 #define OHCI_TD_NOCC 0xf0000000 201 #define OHCI_TD_ALIGN 16 203 #define OHCI_ITD_NOFFSET 8 206 #define OHCI_ITD_GET_SF(x) ((x) & 0x0000ffff) 207 #define OHCI_ITD_SET_SF(x) ((x) & 0xffff) 208 #define OHCI_ITD_GET_DI(x) (((x) >> 21) & 7) 209 #define OHCI_ITD_SET_DI(x) ((x) << 21) 210 #define OHCI_ITD_NOINTR 0x00e00000 211 #define OHCI_ITD_GET_FC(x) ((((x) >> 24) & 7)+1) 212 #define OHCI_ITD_SET_FC(x) (((x)-1) << 24) 213 #define OHCI_ITD_GET_CC(x) ((x) >> 28) 214 #define OHCI_ITD_NOCC 0xf0000000 219 #define itd_pswn itd_offset 220 #define OHCI_ITD_PAGE_SELECT 0x00001000 221 #define OHCI_ITD_MK_OFFS(len) (0xe000 | ((len) & 0x1fff)) 222 #define OHCI_ITD_PSW_LENGTH(x) ((x) & 0xfff) 223 #define OHCI_ITD_PSW_GET_CC(x) ((x) >> 12) 226 #define OHCI_ITD_ALIGN 32 229 #define OHCI_CC_NO_ERROR 0 230 #define OHCI_CC_CRC 1 231 #define OHCI_CC_BIT_STUFFING 2 232 #define OHCI_CC_DATA_TOGGLE_MISMATCH 3 233 #define OHCI_CC_STALL 4 234 #define OHCI_CC_DEVICE_NOT_RESPONDING 5 235 #define OHCI_CC_PID_CHECK_FAILURE 6 236 #define OHCI_CC_UNEXPECTED_PID 7 237 #define OHCI_CC_DATA_OVERRUN 8 238 #define OHCI_CC_DATA_UNDERRUN 9 239 #define OHCI_CC_BUFFER_OVERRUN 12 240 #define OHCI_CC_BUFFER_UNDERRUN 13 241 #define OHCI_CC_NOT_ACCESSED 15 244 #define OHCI_ENABLE_POWER_DELAY 5 245 #define OHCI_READ_DESC_DELAY 5 ohci_physaddr_t ed_nexted
u_int32_t ohci_physaddr_t
ohci_physaddr_t hcca_interrupt_table[OHCI_NO_INTRS]
ohci_physaddr_t hcca_done_head
ohci_physaddr_t td_nexttd
u_int32_t hcca_frame_number
ohci_physaddr_t itd_nextitd