clmpccreg.h Source File
Back to the index.
Go to the documentation of this file. 60 #define CLMPCC_FIFO_DEPTH 16 63 #define CLMPCC_REG_GFRCR 0x81 64 #define CLMPCC_REG_CAR 0xee 67 #define CLMPCC_REG_CMR 0x1b 68 #define CLMPCC_REG_COR1 0x10 69 #define CLMPCC_REG_COR2 0x17 70 #define CLMPCC_REG_COR3 0x16 71 #define CLMPCC_REG_COR4 0x15 72 #define CLMPCC_REG_COR5 0x14 73 #define CLMPCC_REG_COR6 0x18 74 #define CLMPCC_REG_COR7 0x07 75 #define CLMPCC_REG_SCHR1 0x1f 76 #define CLMPCC_REG_SCHR2 0x1e 77 #define CLMPCC_REG_SCHR3 0x1d 78 #define CLMPCC_REG_SCHR4 0x1c 79 #define CLMPCC_REG_SCRl 0x23 80 #define CLMPCC_REG_SCRh 0x22 81 #define CLMPCC_REG_LNXT 0x2e 82 #define CLMPCC_REG_RFAR1 0x1f 83 #define CLMPCC_REG_RFAR2 0x1e 84 #define CLMPCC_REG_RFAR3 0x1d 85 #define CLMPCC_REG_RFAR4 0x1c 86 #define CLMPCC_REG_CPSR 0xd6 89 #define CLMPCC_REG_RBPR 0xcb 90 #define CLMPCC_REG_RCOR 0xc8 91 #define CLMPCC_REG_TBPR 0xc3 92 #define CLMPCC_REG_TCOR 0xc0 95 #define CLMPCC_REG_CCR 0x13 96 #define CLMPCC_REG_STCR 0x12 97 #define CLMPCC_REG_CSR 0x1a 98 #define CLMPCC_REG_MSVR 0xde 99 #define CLMPCC_REG_MSVR_RTS 0xde 100 #define CLMPCC_REG_MSVR_DTR 0xdf 103 #define CLMPCC_REG_LIVR 0x09 104 #define CLMPCC_REG_IER 0x11 105 #define CLMPCC_REG_LICR 0x26 106 #define CLMPCC_REG_STK 0xe2 109 #define CLMPCC_REG_RPILR 0xe1 110 #define CLMPCC_REG_RIR 0xed 111 #define CLMPCC_REG_RISR 0x88 112 #define CLMPCC_REG_RISRl 0x89 113 #define CLMPCC_REG_RISRh 0x88 114 #define CLMPCC_REG_RFOC 0x30 115 #define CLMPCC_REG_RDR 0xf8 116 #define CLMPCC_REG_REOIR 0x84 119 #define CLMPCC_REG_TPILR 0xe0 120 #define CLMPCC_REG_TIR 0xec 121 #define CLMPCC_REG_TISR 0x8a 122 #define CLMPCC_REG_TFTC 0x80 123 #define CLMPCC_REG_TDR 0xf8 124 #define CLMPCC_REG_TEOIR 0x85 127 #define CLMPCC_REG_MPILR 0xe3 128 #define CLMPCC_REG_MIR 0xef 129 #define CLMPCC_REG_MISR 0x8b 130 #define CLMPCC_REG_MEOIR 0x86 133 #define CLMPCC_REG_DMR 0xf6 134 #define CLMPCC_REG_BERCNT 0x8e 135 #define CLMPCC_REG_DMABSTS 0x19 138 #define CLMPCC_REG_ARBADRL 0x42 139 #define CLMPCC_REG_ARBADRU 0x40 140 #define CLMPCC_REG_BRBADRL 0x46 141 #define CLMPCC_REG_BRBADRU 0x44 142 #define CLMPCC_REG_ARBCNT 0x4a 143 #define CLMPCC_REG_BRBCNT 0x48 144 #define CLMPCC_REG_ARBSTS 0x4f 145 #define CLMPCC_REG_BRBSTS 0x4e 146 #define CLMPCC_REG_RCBADRL 0x3e 147 #define CLMPCC_REG_RCBADRU 0x3c 150 #define CLMPCC_REG_ATBADRL 0x52 151 #define CLMPCC_REG_ATBADRU 0x50 152 #define CLMPCC_REG_BTBADRL 0x56 153 #define CLMPCC_REG_BTBADRU 0x54 154 #define CLMPCC_REG_ATBCNT 0x5a 155 #define CLMPCC_REG_BTBCNT 0x58 156 #define CLMPCC_REG_ATBSTS 0x5f 157 #define CLMPCC_REG_BTBSTS 0x5e 158 #define CLMPCC_REG_TCBADRL 0x3a 159 #define CLMPCC_REG_TCBADRU 0x38 162 #define CLMPCC_REG_TPR 0xda 163 #define CLMPCC_REG_RTPR 0x24 164 #define CLMPCC_REG_RTPRl 0x25 165 #define CLMPCC_REG_RTPRh 0x24 166 #define CLMPCC_REG_GT1 0x2a 167 #define CLMPCC_REG_GT1l 0x2b 168 #define CLMPCC_REG_GT1h 0x2a 169 #define CLMPCC_REG_GT2 0x29 170 #define CLMPCC_REG_TTR 0x29 174 #define CLMPCC_CAR_MASK 0x03 177 #define CLMPCC_CMR_RX_INT (0 << 7) 178 #define CLMPCC_CMR_RX_DMA (1 << 7) 179 #define CLMPCC_CMR_TX_INT (0 << 6) 180 #define CLMPCC_CMR_TX_DMA (1 << 6) 181 #define CLMPCC_CMR_HDLC 0x00 182 #define CLMPCC_CMR_BISYNC 0x01 183 #define CLMPCC_CMR_ASYNC 0x02 184 #define CLMPCC_CMR_X21 0x03 187 #define CLMPCC_COR1_EVEN_PARITY (0 << 7) 188 #define CLMPCC_COR1_ODD_PARITY (1 << 7) 189 #define CLMPCC_COR1_NO_PARITY (0 << 5) 190 #define CLMPCC_COR1_FORCE_PAR (1 << 5) 191 #define CLMPCC_COR1_NORM_PARITY (2 << 5) 192 #define CLMPCC_COR1_CHECK_PAR (0 << 4) 193 #define CLMPCC_COR1_IGNORE_PAR (1 << 4) 194 #define CLMPCC_COR1_CHAR_5BITS 0x04 195 #define CLMPCC_COR1_CHAR_6BITS 0x05 196 #define CLMPCC_COR1_CHAR_7BITS 0x06 197 #define CLMPCC_COR1_CHAR_8BITS 0x07 200 #define CLMPCC_COR2_IXM (1 << 7) 201 #define CLMPCC_COR2_TxIBE (1 << 6) 202 #define CLMPCC_COR2_ETC (1 << 5) 203 #define CLMPCC_COR2_RLM (1 << 3) 204 #define CLMPCC_COR2_RtsAO (1 << 2) 205 #define CLMPCC_COR2_CtsAE (1 << 1) 206 #define CLMPCC_COR2_DsrAE (1 << 1) 209 #define CLMPCC_ETC_MAGIC 0x00 210 #define CLMPCC_ETC_SEND_BREAK 0x81 211 #define CLMPCC_ETC_DELAY 0x82 212 #define CLMPCC_ETC_STOP_BREAK 0x83 215 #define CLMPCC_COR3_ESCDE (1 << 7) 216 #define CLMPCC_COR3_RngDE (1 << 6) 217 #define CLMPCC_COR3_FCT (1 << 5) 218 #define CLMPCC_COR3_SCDE (1 << 4) 219 #define CLMPCC_COR3_SpIstp (1 << 3) 220 #define CLMPCC_COR3_STOP_1 0x02 221 #define CLMPCC_COR3_STOP_1_5 0x03 222 #define CLMPCC_COR3_STOP_2 0x04 225 #define CLMPCC_COR4_DSRzd (1 << 7) 226 #define CLMPCC_COR4_CDzd (1 << 6) 227 #define CLMPCC_COR4_CTSzd (1 << 5) 228 #define CLMPCC_COR4_FIFO_MASK 0x0f 229 #define CLMPCC_COR4_FIFO_LOW 1 230 #define CLMPCC_COR4_FIFO_MED 4 231 #define CLMPCC_COR4_FIFO_HIGH 8 234 #define CLMPCC_COR5_DSRod (1 << 7) 235 #define CLMPCC_COR5_CDod (1 << 6) 236 #define CLMPCC_COR5_CTSod (1 << 5) 237 #define CLMPCC_COR5_FLOW_MASK 0x0f 238 #define CLMPCC_COR5_FLOW_NORM 8 241 #define CLMPCC_COR6_RX_CRNL 0x00 242 #define CLMPCC_COR6_BRK_EXCEPT (0 << 3) 243 #define CLMPCC_COR6_BRK_2_NULL (1 << 3) 244 #define CLMPCC_COR6_BRK_DISCARD (3 << 3) 245 #define CLMPCC_COR6_PF_EXCEPT 0x00 246 #define CLMPCC_COR6_PF_2_NULL 0x01 247 #define CLMPCC_COR6_PF_IGNORE 0x02 248 #define CLMPCC_COR6_PF_DISCARD 0x03 249 #define CLMPCC_COR6_PF_TRANS 0x05 252 #define CLMPCC_COR7_ISTRIP (1 << 7) 253 #define CLMPCC_COR7_LNE (1 << 6) 254 #define CLMPCC_COR7_FCERR (1 << 5) 255 #define CLMPCC_COR7_TX_CRNL 0x00 258 #define CLMPCC_RCOR_CLK(x) (x) 259 #define CLMPCC_RCOR_TLVAL (1 << 7) 260 #define CLMPCC_RCOR_DPLL_ENABLE (1 << 5) 261 #define CLMPCC_RCOR_DPLL_NRZ (0 << 3) 262 #define CLMPCC_RCOR_DPLL_NRZI (1 << 3) 263 #define CLMPCC_RCOR_DPLL_MAN (2 << 3) 264 #define CLMPCC_RCOR_CLK_0 0x0 265 #define CLMPCC_RCOR_CLK_1 0x1 266 #define CLMPCC_RCOR_CLK_2 0x2 267 #define CLMPCC_RCOR_CLK_3 0x3 268 #define CLMPCC_RCOR_CLK_4 0x4 269 #define CLMPCC_RCOR_CLK_EXT 0x6 272 #define CLMPCC_TCOR_CLK(x) ((x) << 5) 273 #define CLMPCC_TCOR_CLK_0 (0 << 5) 274 #define CLMPCC_TCOR_CLK_1 (1 << 5) 275 #define CLMPCC_TCOR_CLK_2 (2 << 5) 276 #define CLMPCC_TCOR_CLK_3 (3 << 5) 277 #define CLMPCC_TCOR_CLK_4 (4 << 5) 278 #define CLMPCC_TCOR_CLK_EXT (6 << 5) 279 #define CLMPCC_TCOR_CLK_RX (7 << 5) 280 #define CLMPCC_TCOR_EXT_1X (1 << 3) 281 #define CLMPCC_TCOR_LOCAL_LOOP (1 << 1) 284 #define CLMPCC_STCR_SSPC(n) ((n) & 0x7) 285 #define CLMPCC_STCR_SND_SPC (1 << 3) 286 #define CLMPCC_STCR_APPEND_COMP (1 << 5) 287 #define CLMPCC_STCR_ABORT_TX (1 << 6) 290 #define CLMPCC_CCR_T0_CLEAR 0x40 291 #define CLMPCC_CCR_T0_INIT 0x20 292 #define CLMPCC_CCR_T0_RESET_ALL 0x10 293 #define CLMPCC_CCR_T0_TX_EN 0x08 294 #define CLMPCC_CCR_T0_TX_DIS 0x04 295 #define CLMPCC_CCR_T0_RX_EN 0x02 296 #define CLMPCC_CCR_T0_RX_DIS 0x01 297 #define CLMPCC_CCR_T1_CLR_TMR1 0xc0 298 #define CLMPCC_CCR_T1_CLR_TMR2 0xa0 299 #define CLMPCC_CCR_T1_CLR_RECV 0x90 302 #define CLMPCC_CSR_RX_ENABLED (1 << 7) 303 #define CLMPCC_CSR_RX_FLOW_OFF (1 << 6) 304 #define CLMPCC_CSR_RX_FLOW_ON (1 << 5) 305 #define CLMPCC_CSR_TX_ENABLED (1 << 3) 306 #define CLMPCC_CSR_TX_FLOW_OFF (1 << 2) 307 #define CLMPCC_CSR_TX_FLOW_ON (1 << 1) 310 #define CLMPCC_MSVR_DSR (1 << 7) 311 #define CLMPCC_MSVR_CD (1 << 6) 312 #define CLMPCC_MSVR_CTS (1 << 5) 313 #define CLMPCC_MSVR_DTR_OPT (1 << 4) 314 #define CLMPCC_MSVR_PORT_ID (1 << 2) 315 #define CLMPCC_MSVR_DTR (1 << 1) 316 #define CLMPCC_MSVR_RTS (1 << 0) 319 #define CLMPCC_LIVR_TYPE_MASK 0x03 320 #define CLMPCC_LIVR_EXCEPTION 0x0 321 #define CLMPCC_LIVR_MODEM 0x1 322 #define CLMPCC_LIVR_TX 0x2 323 #define CLMPCC_LIVR_RX 0x3 326 #define CLMPCC_IER_MODEM (1 << 7) 327 #define CLMPCC_IER_RET (1 << 5) 328 #define CLMPCC_IER_RX_FIFO (1 << 3) 329 #define CLMPCC_IER_TIMER (1 << 2) 330 #define CLMPCC_IER_TX_EMPTY (1 << 1) 331 #define CLMPCC_IER_TX_FIFO (1 << 0) 334 #define CLMPCC_LICR_MASK 0x0c 335 #define CLMPCC_LICR_CHAN(v) (((v) & CLMPCC_LICR_MASK) >> 2) 338 #define CLMPCC_RIR_REN (1 << 7) 339 #define CLMPCC_RIR_RACT (1 << 6) 340 #define CLMPCC_RIR_REOI (1 << 5) 341 #define CLMPCC_RIR_RCVT_MASK 0x0c 342 #define CLMPCC_RIR_RCN_MASK 0x03 345 #define CLMPCC_RISR_TIMEOUT (1 << 7) 346 #define CLMPCC_RISR_OVERRUN (1 << 3) 347 #define CLMPCC_RISR_PARITY (1 << 2) 348 #define CLMPCC_RISR_FRAMING (1 << 1) 349 #define CLMPCC_RISR_BREAK (1 << 0) 352 #define CLMPCC_RFOC_MASK 0x1f 355 #define CLMPCC_REOIR_TERMBUFF (1 << 7) 356 #define CLMPCC_REOIR_DIS_EX_CHR (1 << 6) 357 #define CLMPCC_REOIR_TMR2_SYNC (1 << 5) 358 #define CLMPCC_REOIR_TMR1_SYNC (1 << 4) 359 #define CLMPCC_REOIR_NO_TRANS (1 << 3) 362 #define CLMPCC_TIR_TEN (1 << 7) 363 #define CLMPCC_TIR_TACT (1 << 6) 364 #define CLMPCC_TIR_TEOI (1 << 5) 365 #define CLMPCC_TIR_TCVT_MASK 0x0c 366 #define CLMPCC_TIR_TCN_MASK 0x03 369 #define CLMPCC_TISR_BERR (1 << 7) 370 #define CLMPCC_TISR_EOF (1 << 6) 371 #define CLMPCC_TISR_EOB (1 << 5) 372 #define CLMPCC_TISR_UNDERRUN (1 << 4) 373 #define CLMPCC_TISR_BUFF_ID (1 << 3) 374 #define CLMPCC_TISR_TX_EMPTY (1 << 1) 375 #define CLMPCC_TISR_TX_FIFO (1 << 0) 378 #define CLMPCC_TFTC_MASK 0x1f 381 #define CLMPCC_TEOIR_TERMBUFF (1 << 7) 382 #define CLMPCC_TEOIR_END_OF_FRM (1 << 6) 383 #define CLMPCC_TEOIR_TMR2_SYNC (1 << 5) 384 #define CLMPCC_TEOIR_TMR1_SYNC (1 << 4) 385 #define CLMPCC_TEOIR_NO_TRANS (1 << 3) 388 #define CLMPCC_MIR_MEN (1 << 7) 389 #define CLMPCC_MIR_MACT (1 << 6) 390 #define CLMPCC_MIR_MEOI (1 << 5) 391 #define CLMPCC_MIR_MCVT_MASK 0x0c 392 #define CLMPCC_MIR_MCN_MASK 0x03 395 #define CLMPCC_MISR_DSR (1 << 7) 396 #define CLMPCC_MISR_CD (1 << 6) 397 #define CLMPCC_MISR_CTS (1 << 5) 398 #define CLMPCC_MISR_TMR2 (1 << 1) 399 #define CLMPCC_MISR_TMR1 (1 << 0) 402 #define CLMPCC_MEOIR_TMR2_SYNC (1 << 5) 403 #define CLMPCC_MEOIR_TMR1_SYNC (1 << 4) 406 #define CLMPCC_RTPR_DEFAULT 2 413 #define CLMPCC_MSEC_TO_TPR(c,m) (((((c)/2048)/(1000/(m))) > 0x0a) ? \ 414 (((c)/2048)/(1000/(m))) : 0x0a)
Generated on Fri Dec 7 2018 19:52:23 for GXemul by
1.8.13