73 #define DEC21143_TICK_SHIFT 16 123 #define MII_STATE_RESET 0 124 #define MII_STATE_START_WAIT 1 125 #define MII_STATE_READ_OP 2 126 #define MII_STATE_READ_PHYADDR_REGADDR 3 127 #define MII_STATE_A 4 128 #define MII_STATE_D 5 129 #define MII_STATE_IDLE 6 142 unsigned char descr[16];
143 uint32_t rdes0, rdes1, rdes2, rdes3;
144 int bufsize, buf1_size, buf2_size, i, writeback_len = 4, to_xfer;
170 if (!cpu->
memory_rw(cpu, cpu->
mem, addr, descr,
sizeof(uint32_t),
172 fatal(
"[ dec21143_rx: memory_rw failed! ]\n");
176 rdes0 = descr[0] + (descr[1]<<8) + (descr[2]<<16) + (descr[3]<<24);
184 if (!cpu->
memory_rw(cpu, cpu->
mem, addr +
sizeof(uint32_t), descr +
187 fatal(
"[ dec21143_rx: memory_rw failed! ]\n");
191 rdes1 = descr[4] + (descr[5]<<8) + (descr[6]<<16) + (descr[7]<<24);
192 rdes2 = descr[8] + (descr[9]<<8) + (descr[10]<<16) + (descr[11]<<24);
193 rdes3 = descr[12] + (descr[13]<<8) + (descr[14]<<16) + (descr[15]<<24);
197 bufaddr = buf1_size? rdes2 : rdes3;
198 bufsize = buf1_size? buf1_size : buf2_size;
211 debug(
"{ RX (%llx): 0x%08x 0x%08x 0x%x 0x%x: buf %i bytes at 0x%x }\n",
212 (
long long)addr, rdes0, rdes1, rdes2, rdes3, bufsize, (
int)bufaddr);
213 bufaddr &= 0x7fffffff;
219 if (to_xfer > bufsize)
223 for (i=0; i<to_xfer; i++) {
256 descr[ 0] = rdes0; descr[ 1] = rdes0 >> 8;
257 descr[ 2] = rdes0 >> 16; descr[ 3] = rdes0 >> 24;
258 if (writeback_len > 1) {
259 descr[ 4] = rdes1; descr[ 5] = rdes1 >> 8;
260 descr[ 6] = rdes1 >> 16; descr[ 7] = rdes1 >> 24;
261 descr[ 8] = rdes2; descr[ 9] = rdes2 >> 8;
262 descr[10] = rdes2 >> 16; descr[11] = rdes2 >> 24;
263 descr[12] = rdes3; descr[13] = rdes3 >> 8;
264 descr[14] = rdes3 >> 16; descr[15] = rdes3 >> 24;
267 if (!cpu->
memory_rw(cpu, cpu->
mem, addr, descr,
sizeof(uint32_t)
269 fatal(
"[ dec21143_rx: memory_rw failed! ]\n");
286 unsigned char descr[16];
287 uint32_t tdes0, tdes1, tdes2, tdes3;
288 int bufsize, buf1_size, buf2_size, i;
292 if (!cpu->
memory_rw(cpu, cpu->
mem, addr, descr,
sizeof(uint32_t),
294 fatal(
"[ dec21143_tx: memory_rw failed! ]\n");
298 tdes0 = descr[0] + (descr[1]<<8) + (descr[2]<<16) + (descr[3]<<24);
313 if (!cpu->
memory_rw(cpu, cpu->
mem, addr +
sizeof(uint32_t), descr +
316 fatal(
"[ dec21143_tx: memory_rw failed! ]\n");
320 tdes1 = descr[4] + (descr[5]<<8) + (descr[6]<<16) + (descr[7]<<24);
321 tdes2 = descr[8] + (descr[9]<<8) + (descr[10]<<16) + (descr[11]<<24);
322 tdes3 = descr[12] + (descr[13]<<8) + (descr[14]<<16) + (descr[15]<<24);
326 bufaddr = buf1_size? tdes2 : tdes3;
327 bufsize = buf1_size? buf1_size : buf2_size;
344 bufaddr &= 0x7fffffff;
358 fatal(
"[ dec21143: setup packet len = %i, should be" 359 " 192! ]\n", (
int)bufsize);
363 tdes0 = 0x7fffffff; tdes1 = 0xffffffff;
364 tdes2 = 0xffffffff; tdes3 = 0xffffffff;
382 fatal(
"[ dec21143: WARNING! tx: middle " 383 "segment, but no first segment?! ]\n");
390 for (i=0; i<bufsize; i++) {
403 if (d->
net != NULL) {
409 fatal(
"[ dec21143: WARNING! Not " 410 "connected to a network! ]\n");
424 tdes0 &= ~TDSTAT_OWN;
433 descr[ 0] = tdes0; descr[ 1] = tdes0 >> 8;
434 descr[ 2] = tdes0 >> 16; descr[ 3] = tdes0 >> 24;
435 descr[ 4] = tdes1; descr[ 5] = tdes1 >> 8;
436 descr[ 6] = tdes1 >> 16; descr[ 7] = tdes1 >> 24;
437 descr[ 8] = tdes2; descr[ 9] = tdes2 >> 8;
438 descr[10] = tdes2 >> 16; descr[11] = tdes2 >> 24;
439 descr[12] = tdes3; descr[13] = tdes3 >> 8;
440 descr[14] = tdes3 >> 16; descr[15] = tdes3 >> 24;
442 if (!cpu->
memory_rw(cpu, cpu->
mem, addr, descr,
sizeof(uint32_t)
444 fatal(
"[ dec21143_tx: memory_rw failed! ]\n");
502 uint32_t oldreg, uint32_t idata)
511 if (idata & MIIROM_MDC && oldreg & MIIROM_MDC)
517 fatal(
"[ mii_access(): MIIROM_BR: TODO ]\n");
526 fatal(
"[ mii_access(): bad dir? ]\n");
534 if (idata & MIIROM_MIIDIR)
547 if (idata & MIIROM_MIIDIR) {
595 default:
debug(
"[ mii_access(): UNIMPLEMENTED MII opcode " 596 "%i (probably just a bug in GXemul's " 597 "MII data stream handling) ]\n", d->
mii_opcode);
606 if (idata & MIIROM_MIIDIR)
607 fatal(
"[ mii_access(): write: bad dir? ]\n");
608 obit = obit? (0x8000 >> (d->
mii_bit - 14)) : 0;
613 debug(
"[ mii_access(): WRITE to phyaddr=0x%x " 619 if (!(idata & MIIROM_MIIDIR))
624 debug(
"[ mii_access(): READ phyaddr=0x%x " 627 ibit = tmp & (0x8000 >> (d->
mii_bit - 13));
667 static void srom_access(
struct cpu *cpu,
struct dec21143_data *d,
668 uint32_t oldreg, uint32_t idata)
715 debug(
"[ dec21143: ROM read from offset" 716 " 0x%03x: 0x%04x ]\n",
718 obit = romword & (0x8000 >>
722 default:
fatal(
"[ dec21243: unimplemented SROM/EEPROM " 751 static void dec21143_reset(
struct cpu *cpu,
struct dec21143_data *d)
761 memset(d->
reg, 0,
sizeof(uint32_t) *
N_REGS);
762 memset(d->
srom, 0,
sizeof(d->
srom));
795 leaf += d->
srom[leaf];
803 leaf += d->
srom[leaf];
817 uint64_t idata = 0, odata = 0;
819 int regnr = relative_addr >> 3;
824 if ((relative_addr & 7) == 0 && regnr <
N_REGS) {
826 odata = d->
reg[regnr];
828 oldreg = d->
reg[regnr];
831 d->
reg[regnr] &= ~(idata & 0x0c01ffff);
835 default:d->
reg[regnr] = idata;
839 fatal(
"[ dec21143: WARNING! unaligned access (0x%x) ]\n",
842 switch (relative_addr) {
848 dec21143_reset(cpu, d);
849 idata &= ~BUSMODE_SWR;
856 fatal(
"[ dec21143: UNIMPLEMENTED READ from " 859 dev_dec21143_tick(cpu, extra);
864 fatal(
"[ dec21143: UNIMPLEMENTED READ from " 866 dev_dec21143_tick(cpu, extra);
871 debug(
"[ dec21143: setting RXLIST to 0x%x ]\n",
874 fatal(
"[ dec21143: WARNING! RXLIST not aligned" 875 "? (0x%llx) ]\n", (
long long)idata);
883 debug(
"[ dec21143: setting TXLIST to 0x%x ]\n",
886 fatal(
"[ dec21143: WARNING! TXLIST not aligned" 887 "? (0x%llx) ]\n", (
long long)idata);
897 dev_dec21143_tick(cpu, extra);
903 if (idata & 0x02000000) {
905 idata &= ~0x02000000;
922 idata &= ~OPMODE_PNIC_IT;
926 fatal(
"[ dec21143: UNIMPLEMENTED OPMODE bits" 927 ": 0x%08x ]\n", (
int)idata);
929 dev_dec21143_tick(cpu, extra);
939 mii_access(cpu, d, oldreg, idata);
941 srom_access(cpu, d, oldreg, idata);
961 fatal(
"[ dec21143: read from unimplemented 0x%02x ]\n",
964 fatal(
"[ dec21143: write to unimplemented 0x%02x: " 965 "0x%02x ]\n", (
int)relative_addr, (
int)idata);
992 snprintf(name2,
sizeof(name2),
"%s [%02x:%02x:%02x:%02x:%02x:%02x]",
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
void net_ethernet_tx(struct net *net, void *extra, unsigned char *packet, int len)
void fatal(const char *fmt,...)
#define MII_STATE_READ_OP
#define TULIP_ROM_SROM_FORMAT_VERION
int dec21143_rx(struct cpu *cpu, struct dec21143_data *d)
#define TDCTL_SIZE2_SHIFT
unsigned char * cur_tx_buf
#define MII_STATE_READ_PHYADDR_REGADDR
#define TULIP_ROM_IL_SELECT_CONN_TYPE
int srom_opcode_has_started
#define TULIP_ROM_MB_21142_MII
int net_ethernet_rx(struct net *net, void *extra, unsigned char **packetp, int *lenp)
#define CHECK_ALLOCATION(ptr)
void net_add_nic(struct net *net, void *extra, unsigned char *macaddr)
int(* memory_rw)(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
unsigned char * cur_rx_buf
int dec21143_tx(struct cpu *cpu, struct dec21143_data *d)
void dev_ram_init(struct machine *machine, uint64_t baseaddr, uint64_t length, int mode, uint64_t otheraddress, const char *name)
#define INTERRUPT_ASSERT(istruct)
void net_generate_unique_mac(struct machine *, unsigned char *macbuf)
#define TULIP_ROM_CHIP_COUNT
int net_ethernet_rx_avail(struct net *net, void *extra)
#define DEC21143_TICK_SHIFT
#define INTERRUPT_CONNECT(name, istruct)
uint16_t mii_phy_reg[MII_NPHY *32]
#define DEV_RAM_MIGHT_POINT_TO_DEVICES
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
#define TULIP_ROM_MB_MEDIA_100TX
#define TULIP_ROM_CHIPn_DEVICE_NUMBER(n)
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
#define MII_COMMAND_WRITE
#define TULIP_ROM_IL_MEDIAn_BLOCK_BASE
#define SIASTAT_ANS_FLPGOOD
#define TULIP_ROM_MB_21142_SIA
#define TULIP_SROM_OPC_READ
addr & if(addr >=0x24 &&page !=NULL)
uint8_t srom[1<<(ROM_WIDTH+1)]
void machine_add_tickfunction(struct machine *machine, void(*func)(struct cpu *, void *), void *extra, int clockshift)
#define MII_STATE_START_WAIT
#define TULIP_ROM_CHIPn_INFO_LEAF_OFFSET(n)
#define TULIP_ROM_IL_MEDIA_COUNT
#define TULIP_ROM_IEEE_NETWORK_ADDRESS
#define INTERRUPT_DEASSERT(istruct)